From patchwork Wed Mar 8 16:39:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 2784 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pj1-f71.google.com (mail-pj1-f71.google.com [209.85.216.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 335FC414B5 for ; Wed, 8 Mar 2023 17:40:45 +0100 (CET) Received: by mail-pj1-f71.google.com with SMTP id h19-20020a17090aa89300b0023a9e52c40dsf4613966pjq.0 for ; Wed, 08 Mar 2023 08:40:45 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678293644; cv=pass; d=google.com; s=arc-20160816; b=Fgp1PIHhjNpRLCYh5NkwuR4vF9uCRU1qOE+Sig6W2rxI/uId3Xwpm0ZdcqdwbIIgbk Xmu6N6JvMhb0RKTEWtbw1vO8V/9z6JWghktMZA2ixVGBtsHnuFqmescSeK9DhiJHWuIl KjqlTrCZoaWBFS3MncVGGlKY3AgfnxoLCf8y0VcsbopNBsYihvI48XssFoxP0Bw5B35U EVMTy58ZpYiqvxvgEN0vW4dv7cKrK9nmO2VHndhBkHRBT9HwQVC4KZB4NXqGgvOGp1i1 oyREdOBcwnqjjId01G1coQKTItsjKtCTrmx2ps3pEYEmbB+w3pzw7Mxfm7WW+360DjQK VCBw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=qlPVFHfdYruQqriYps7QnWzI8Q6XLTKR0xj6d2XABPw=; b=cMLQ8d/hbMp/9nwS090zaNvFOYRk01Tb8aN69020zc9b91C5XIrV8WZOqahnfjGpgn JvXfW+Ggqe/bvxycL0S+nA+wrgJ8awe0Jd6S2VaxN51hw1uA6deyMNEOMiFgAcW2XFbz KWLJt+/zThf1tykjrCWocjcBa2/Gx7QYgpimo66qVRcjIOiX5mIoZK+B4PlSTQpFxOvi 32z/q6UElo8J/i0xRjSkCnte6PUJK2Un3BKMd1RQ4Iob1hUp/kME5sxleNq0CcQeg66k PjcacPeCholWNVEgc9FXB1z/3xS1mH5lr35JODmfsHcwekSYS+gy+oMm6sr/dsMieaTZ eHLQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SV94dmfQ; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1678293644; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=qlPVFHfdYruQqriYps7QnWzI8Q6XLTKR0xj6d2XABPw=; b=XXWZtPQICxblSmwUB9JTqsGH9RfV1TvEBK/VIZRva3PwguDYukmQTU8cpbjFDnEEoz QR5rK7mW4MnpgRx5fgA9+DPVY/bOeVJ2KYTYEIgkmyy9vENinBTpfU6JQ9qUeBZtcfpz zplUOU9ivU2mcif4xO0TdwbyDOZ4j2AbUSjWM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678293644; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qlPVFHfdYruQqriYps7QnWzI8Q6XLTKR0xj6d2XABPw=; b=30kQ6N9JBGKqbXDYFXPQrXzeKXZt2HrFeiH/P10NOGyMxu8oKH4XL2QWpsHxQ537H2 iPU+5cVboU56qszARaS8ps40MN9k+/3lrvICCVdMHcJsutNE0SQwjN5UUavBm+Icw48g OGOHB+dwWxmm6ZEVOAg1dhcDH15uVAS1srFko+qYAhEC7sVRz0NlyItr69OS6wOIjUqt eOPPNzY6xgNECVPs1qCgTHKO0SbSG51XAwcwLj1jG+6aCvaxhN3iWZ3PjC+g+MjcZYYc Gn7oPRH5xioLX+GZC84g7uzmeIZa8XiXMIWM7NUzwbK10G+zH92iIUjciPUkIhj9OphH fjgQ== X-Gm-Message-State: AO0yUKU6jDu6wdoew7iwYPsuAw2/mgdFXGEBWE2Y6LriO+YDsBv8geLo bGRg9Eu4V4qyGKQ7Jg/VU6DJz9Ee X-Google-Smtp-Source: AK7set8/KJMm2CrDiT0ne0f6CzH6iEQij82V9BIxryHIi0jBAeSXNRvacxTx+SB0n5T5rCiDF85FZg== X-Received: by 2002:a17:90a:f404:b0:234:b29d:3319 with SMTP id ch4-20020a17090af40400b00234b29d3319mr6929079pjb.8.1678293643803; Wed, 08 Mar 2023 08:40:43 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:be18:b0:199:50f5:6729 with SMTP id r24-20020a170902be1800b0019950f56729ls16323111pls.11.-pod-prod-gmail; Wed, 08 Mar 2023 08:40:43 -0800 (PST) X-Received: by 2002:a17:903:41c3:b0:19c:e449:bbaa with SMTP id u3-20020a17090341c300b0019ce449bbaamr22572549ple.28.1678293642808; Wed, 08 Mar 2023 08:40:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678293642; cv=none; d=google.com; s=arc-20160816; b=qmFMAtSCzijbWz1KcraF8zstKKYTEZFlYJXJEwjwURVyK6kCQ6IgtZK7sfmtPSmNZN aId44D17x/1y7LnamC3HIfv6XYXD96tdQjR7gENdh43JLbH7f/uxxpTQboeUTEFY4Emd sv0Ddn7Pvb2X6MJpWhWJmxgwQwvzpOmKUfxL+rFghnyvODAFI1QIwVo2VEQze2foxTHd QnkxgvYzrJyW4Y1gHdUjOW8HYg1cUaOTNLbDEjZeHfQB9CrA34gRrbAx7usGWRJ9ouz1 ymOCcgJPo8fsJ8t7Bf4/CDN5sH0TZw1byyh9Swbz+XjeMMw9WUZ3quu1CwsDn+iH21Kv YxoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4/ZpRoWlscQf7x650G5ocJj9fBh6agMK8aXNyTthMvo=; b=t2W7ANraVNMet+JhUl8QjnWsXchzIlGjWjhEjmyi+xvT67LaL4OQtuDZZwyG5axtyU kG4LAANFrRjIC7glmC4+uD3D08Vr1vvlyyEH64kQYPJxbsuAnijrRUlTdKtki2dYi1AL N3Elm4SPxupD3hBe2DhIuS2aTXm2h3d5oAEtC34550TeJDjVLulLP8k28L5hRpvzVT8k IsFnbaF1GXH+cIoe/YCHut4X5tF4C9Z8/rhYkbI2Zhbvoce0ZZRaBq1m24hyrHxlTwXy HIEVAslkUngvgg3rDPJbUor6QytboEv/wHmBcHemtJc9KiNAJZR4jMScsw+XPI1iif/q iwtA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SV94dmfQ; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id ix13-20020a170902f80d00b00195ffe06442sor7998120plb.2.2023.03.08.08.40.42 for (Google Transport Security); Wed, 08 Mar 2023 08:40:42 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:902:d353:b0:19e:2e6b:142e with SMTP id l19-20020a170902d35300b0019e2e6b142emr18567080plk.63.1678293642497; Wed, 08 Mar 2023 08:40:42 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a8a1:b545:91cc:80b2:f9fe]) by smtp.gmail.com with ESMTPSA id kq3-20020a170903284300b0019b9a075f1fsm10046540plb.80.2023.03.08.08.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 08:40:41 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v16 04/16] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Date: Wed, 8 Mar 2023 22:09:41 +0530 Message-Id: <20230308163953.28506-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230308163953.28506-1-jagan@amarulasolutions.com> References: <20230308163953.28506-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=SV94dmfQ; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 Tested-by: Marek Szyprowski Reviewed-by: Marek Vasut Signed-off-by: Frieder Schrempf Signed-off-by: Jagan Teki --- Changes for v16: - collect TB from Marek S Changes for v15, v13, v12, v11, v10, v9: - none Changes for v8: - updated commit message for 8M Nano/Plus Changes for v7, v6: - none Changes for v5: - updated clear commit message Changes for v4, v3, v2: - none Changes for v1: - updated commit message - add downstream driver link drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 1615640e25d6..90ff40af005c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -194,7 +194,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -263,6 +263,7 @@ struct exynos_dsi_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; }; @@ -471,6 +472,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -483,6 +485,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -493,6 +496,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -504,6 +508,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, }; @@ -515,6 +520,7 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, }; @@ -628,7 +634,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = {