From patchwork Sat Apr 22 14:11:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2864 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 01F8E3F334 for ; Sat, 22 Apr 2023 16:11:30 +0200 (CEST) Received: by mail-ed1-f71.google.com with SMTP id 4fb4d7f45d1cf-506a455ee4csf2413278a12.3 for ; Sat, 22 Apr 2023 07:11:30 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1682172689; cv=pass; d=google.com; s=arc-20160816; b=qot1OWPjxQgHG+P9dYjgcn8lriGTF3gmXrlBNtB2Mg2lveypGflenLKzxDSVWy38iT bEFOSfOttg4SlymSwhudJslUPc36KZjE4MKGjp+KQ6xw6VrZCnshNFcnYlJ8wtPlS+Ox 1HxFAZOoHUo0ajE3+13cckyCXJ64Bo0B+cxiTVik4/vXpx3byJqpubfUUyH/V/yNPtlY rsZVgyVAKgkVLLKvLbeCodJXD2ABXp2mr/e2/8uQd/sigioLY7+vkro4DrxCbgiDqjRu +OC5j01l9OM8LtwwpD/2tFVnQUYFandRM6vvT35269iw9QyyktR/itRihxXZEK58OtNT 3+OA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Vi8Ly+HApIjVbOduJvNlDhRMTkyTKzTyX/5VnJdUjiQ=; b=HxKWno88YH1zTYmFMiddkc8R6N0uqROX3AtxS7pTIu0H4b4h9+9jR0JbGAzQelESdI FDsKpE8LaMIOhPxWD0fgrFFj9wSWvHOyjiheS24vwHGWWAz4Kl9Mptkwgmlm+HtbrUi5 KniPl8g4V1s1pEfCpS/fzyYT8Q/pgbXqIoHwTOvkoK2NL+fu6LD+Zqt8tSrJ9WOXFuJx iILt6AeMAzDQCQlflOq/qAP+fI02vjsW+NakLVZ0WZoH2k/yu3uTRUkgHhM+w0yexo5X Mx9KHaBet1DSo9aBZuf+KTQC/D/CqEqB+Q+YDv19QXXEarBOgcC8JTA73blgWFGCMZnw wV6g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hJMK6db1; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682172689; x=1684764689; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=Vi8Ly+HApIjVbOduJvNlDhRMTkyTKzTyX/5VnJdUjiQ=; b=bLvgSQPUEL+23qr3N56HuEsH6mqQcOqSqF5/BZ2x7DN6/W3bnCmP3FVB64aPKLLsvq Bzue6FA2GUAbfhfp/eCo1n4X9fIQI4i2PIJcase+iYWbHwVZCPyexStVEACpJNjJFWp/ /7ZLbjXLD9pGTzlMtgBdYqRR02H8ETcTahuEg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682172689; x=1684764689; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Vi8Ly+HApIjVbOduJvNlDhRMTkyTKzTyX/5VnJdUjiQ=; b=cKV3jxUlme+jwmloz2nC4EhQjHyvb5/P5jKUQfFgxcldth9TMKunsQKFw7hCbO7Vr+ C7mJYmpebBlDourKXbYN0j9cFVp9MDKT57HbQHND0feV9UrQGM+N0YQvu2FT6RubDuR7 37hLyGc/u7Xz2uer9Mc8oigCTTH57HuB3wqzPrnmkkmeJx3YwPEOWYCtBUHmJeccYaDZ UtqWEzWiEj29Pl5xhEoZgtQ9H8aeFicWYmYljtIe1mazoWFNMjdywHQ7Y6gV7TKCh5AK 7WfuCcMp7OWWNdz4fpK2+9v5UzEzOIrsf2plnZ8kRxWoGWvH4ha/B1hTzauZmhK5Xw/r K7AQ== X-Gm-Message-State: AAQBX9cuQ6kqq+NuaGv/1V4R26zbqdFc7oaSE39kPWTGcyhx0dRX8v8A L1mMoc0QSZq2fyMVcATjP22u/sEK7ZEU3iTN X-Google-Smtp-Source: AKy350aYryPQaMMsQY1MiKwxwO1WOS97omdiL7maXizhHT8exCjVTBO5jaBdag3hYexvZ5ojTTrgIg== X-Received: by 2002:a50:a456:0:b0:502:4c87:7981 with SMTP id v22-20020a50a456000000b005024c877981mr3376926edb.4.1682172689723; Sat, 22 Apr 2023 07:11:29 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:906:b14f:b0:94e:d85f:f87f with SMTP id bt15-20020a170906b14f00b0094ed85ff87fls5018522ejb.8.-pod-prod-gmail; Sat, 22 Apr 2023 07:11:28 -0700 (PDT) X-Received: by 2002:a17:906:3550:b0:957:12b6:8918 with SMTP id s16-20020a170906355000b0095712b68918mr5064130eja.75.1682172688165; Sat, 22 Apr 2023 07:11:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682172688; cv=none; d=google.com; s=arc-20160816; b=ZTPoFnT2xQqasBWrU2Ilygm066FV1fgmkcbeFe7LXp3yI6HqNfKQGBqx3TzIwiGbi1 2zcnkijbX64RyahyQj2OiNwUlEngE27B5uhEJ2L9pJUOsM8547r6CcQnnI1yPuyGws3r 29JQGP+wOU8GwOQLV2tpZcS60O1ix1yJgIlI4dGg7JKpEmYhoyn8UWqna/OUnzWmeXKh D3ATyBr9tGl7FoaDWvzohhtUbAsOcbkiJWPStEe35PT+pQ7TAOhClzPBMiD3C/d6j2Ig RaC+MZyHC1bcXRbjnNJnUREByG9jS26SP0AidaAmORuP/D7hvRwFS//VrHkkvQVnKJfP TdYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=D3tGtLKpDPlhoXjnIon7451qNLLQ+gU5NIRQzHhHXZM=; b=drUDFo4tGy+Hswtt21Q7Y7DNjpVwKMlvZygzecTaOV6KXPQckmoyexEiC+PZhQINi7 PS/a6DCh/5WrROvn7c3PHbLtSAVeT7rjEpbYVu5R2N5GJb3s0SlOJwZYNNo9d29Naypa 68lNVi27ghAfdMEL+YPITd52ie26e+oGoQcP8fuTN2/VRQiDhAN154eAxB/lxHUmEafC mRzW1KwDrdB4mesUHzW13s0X22+jTJ6mbkqm6Bk5ysKPQL0zL2EjlgBrbNKiJCG52YC/ IKkebGIpihVGXCCO49KgUoqflkxysHzod4ycg712viAcBmlcXiW3WVMwd2dL/opvXlRf h6hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hJMK6db1; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id ku20-20020a170907789400b0094f190f46ebsor3860327ejc.32.2023.04.22.07.11.28 for (Google Transport Security); Sat, 22 Apr 2023 07:11:28 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:906:35c6:b0:94a:9c9e:6885 with SMTP id p6-20020a17090635c600b0094a9c9e6885mr5071461ejb.58.1682172687850; Sat, 22 Apr 2023 07:11:27 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-99-194.retail.telecomitalia.it. [87.5.99.194]) by smtp.gmail.com with ESMTPSA id de23-20020a1709069bd700b0094f02ebedf5sm3304752ejc.64.2023.04.22.07.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 07:11:27 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: linux-amarula@amarulasolutions.com, Sean Anderson , Lukasz Majewski , Dario Binacchi , Fabio Estevam , Michael Trimarchi , "NXP i.MX U-Boot Team" , Stefano Babic Subject: [RESEND PATCH 2/3] imx6: clock: add support to get LCD pixel clock rate Date: Sat, 22 Apr 2023 16:11:18 +0200 Message-Id: <20230422141119.618453-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230422141119.618453-1-dario.binacchi@amarulasolutions.com> References: <20230422141119.618453-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=hJMK6db1; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the get_lcd_clk() function to get the LCD pixel clock rate. The patch has been tested on imx6ul platform. Signed-off-by: Dario Binacchi --- arch/arm/include/asm/arch-mx6/clock.h | 2 + arch/arm/mach-imx/mx6/clock.c | 58 +++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 8ae49715789c..81af89c631f5 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -41,6 +41,8 @@ enum mxc_clock { MXC_SATA_CLK, MXC_NFC_CLK, MXC_I2C_CLK, + MXC_LCDIF1_CLK, + MXC_LCDIF2_CLK, }; enum ldb_di_clock { diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 17d8dcd5c841..267d86ab4194 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -418,6 +418,60 @@ static u32 get_uart_clk(void) return freq / (uart_podf + 1); } +static u32 get_lcd_clk(unsigned int ifnum) +{ + u32 pll_rate; + u32 pred, postd; + + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() && + !is_mx6sll()) { + debug("This chip does't support lcd\n"); + return 0; + } + + pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK); + if (ifnum == 1) { + if (!is_mx6sl()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cbcmr); + postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } else { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET; + postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET; + } + } else if (ifnum == 2) { + if (is_mx6sx()) { + pred = __raw_readl(&imx_ccm->cscdr2); + pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK; + pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET; + + postd = readl(&imx_ccm->cscmr1); + postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK; + postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET; + + } else { + goto if_err; + } + } else { + goto if_err; + } + + return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1)); + +if_err: + debug("This chip not support lcd iterface %d\n", ifnum); + return 0; +} + static u32 get_cspi_clk(void) { u32 reg, cspi_podf; @@ -1273,6 +1327,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_usdhc_clk(3); case MXC_SATA_CLK: return get_ahb_clk(); + case MXC_LCDIF1_CLK: + return get_lcd_clk(1); + case MXC_LCDIF2_CLK: + return get_lcd_clk(2); default: printf("Unsupported MXC CLK: %d\n", clk); break;