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([37.159.119.249]) by smtp.gmail.com with ESMTPSA id j32-20020a05600c1c2000b003f173987ec2sm13511653wms.22.2023.04.23.10.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 10:25:39 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Lee Jones , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/4] dt-bindings: mfd: stm32f7: add binding definition for CAN3 Date: Sun, 23 Apr 2023 19:25:25 +0200 Message-Id: <20230423172528.1398158-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> References: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=JADuU+he; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add binding definition for CAN3 peripheral. Signed-off-by: Dario Binacchi --- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index a90f3613c584..8d73a9c51e2b 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -64,6 +64,7 @@ #define STM32F7_RCC_APB1_TIM14 8 #define STM32F7_RCC_APB1_LPTIM1 9 #define STM32F7_RCC_APB1_WWDG 11 +#define STM32F7_RCC_APB1_CAN3 13 #define STM32F7_RCC_APB1_SPI2 14 #define STM32F7_RCC_APB1_SPI3 15 #define STM32F7_RCC_APB1_SPDIFRX 16