From patchwork Sun Apr 23 17:25:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 2868 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 10F053F259 for ; Sun, 23 Apr 2023 19:25:44 +0200 (CEST) Received: by mail-wm1-f70.google.com with SMTP id 5b1f17b1804b1-3f16ef3be6esf20898755e9.3 for ; Sun, 23 Apr 2023 10:25:44 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1682270743; cv=pass; d=google.com; s=arc-20160816; b=mRNWRG5hYvfLm4O88iB3EzMnzR5qBayjfB9FBKoQhORaxXNFioEMua8X74hu/ftMra joxp1trRZvwQXsfNm9Cn8/brUH6engomMqxBI7vf7d9tVF7M1gi1gK9kRxT6V8YIeHgo yt/7dyPX2emk+aN6bvYhWACKx8+LMCgpzJebXRYuNnWqnHF/JUuUmPc7QTd5Id+soHOy aO/5iAHZWQQpbb2V4vg17Pg0vNX6pDqN8R3xwMqiZ8G5ZsBBM55a7RJhEMC+eIlwfklw qD4nnwWbB4/SrNPxQPcIDjIIkayUfYKgPgdpuZDmfdbytH8twGKM0mk9WIyMV0jHNgsv gChw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=UG59UemnRMDLHYqmEdQFrLqJ4qMGj9gGIjwjdK+wvPQ=; b=oUsNgzhznBZ6GOSrbF/2yxGY53B8+3R98Czvn2orBHbGWbQCwS6Mu1bKTJppyWWA+S gY5+3ZGvDTgXzZmXLj+O7OkOOEnatj6O8v8/Lz4OV+ItdguUk+EMmAvh7SWHR6Zw/UHv 3kKw4u7Afndt2z2ucdNqynxHe4Hyog1LNeYgn4f2Bx5Q/frSZJ+j/kheplI9hbKAhYmU BpaVfjYqYrfbFKZ8ytlrsHQBNf0ZzVAho7j6+DTdTSaLKO66TGf29Kn5/b8DC2riJUp7 hIYJD2op2acOGv2adS+wMLwNWSfs5TygXrV8h59QN6CkpFeGsaIUp+1dAAjDP71WQK8I qN5w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Ji3b5vRx; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682270743; x=1684862743; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=UG59UemnRMDLHYqmEdQFrLqJ4qMGj9gGIjwjdK+wvPQ=; b=IG4RHxc/Bojh4i4quaTlxdCghLBenKIOl5THFev2dgCSExc7te5PDYbH3OBgianrj4 PA85mLqtkSQHxSkZoNZqQuo20GmqltTU0OoY/OISaIry20KmvC+Naxl20M2skc87SuAR urEDPtvOFEXN6P51N14Y/yzvRnp93YwTOFwNw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682270743; x=1684862743; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UG59UemnRMDLHYqmEdQFrLqJ4qMGj9gGIjwjdK+wvPQ=; b=byD/5cL9IThw+1xxaiHndVm8ydQEG2aZF1zsVr+wWgyWxc76jY1V/Xm+1wTCr2H0l6 MjP2ebh04XzoDjryIBosTvEJKTsPJlKN+NriDIRjKGSelsBuCF6yXmTjquRVFrr+ANz6 W4tN0Tftz5MOoLY2JjS41hvMhuxA5Dn8MirMSikepbm02+gQahlMQAWlq8Rfdc+4HKsN jue+/7qH0Nba0S3j76m10PfpWMyW1KeGh+iCeiR9YTa+P5BUS/y4suKQI7sryRRIAU6d g7bCifTjDQPJrozKBvKBYHw18J6JApYgYrnb/21EzJEX30WUt+bG6Pyr90weS/L3AHG3 fh5Q== X-Gm-Message-State: AAQBX9d91tZImm3ALu8/bkzSqshexvaiHJfOdalW2EPjokT1MRSwe/Rv bw5Nt+afjS7xM1n5mfT/6ui1iMAF18q1pWZL X-Google-Smtp-Source: AKy350Z+GdzDbWv9wC+Jz23P9SeBGaUYYPM6p9/d6jsDBDSrgyjhPLSIlVxoRmfyGh4oo+SbXeJdeQ== X-Received: by 2002:a05:600c:2194:b0:3f1:6f3f:485d with SMTP id e20-20020a05600c219400b003f16f3f485dmr1490068wme.3.1682270743719; Sun, 23 Apr 2023 10:25:43 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a5d:4d8a:0:b0:2f4:1b04:ed8f with SMTP id b10-20020a5d4d8a000000b002f41b04ed8fls14083987wru.1.-pod-prod-gmail; Sun, 23 Apr 2023 10:25:42 -0700 (PDT) X-Received: by 2002:adf:e683:0:b0:2f9:cee4:b8e with SMTP id r3-20020adfe683000000b002f9cee40b8emr7402238wrm.68.1682270742329; Sun, 23 Apr 2023 10:25:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682270742; cv=none; d=google.com; s=arc-20160816; b=yPBPDyH8vnnnI+gw6OKE1XW2mDDJKBol4BQPK7lsxA/WVjSSul3pOxUcA8PsgokUvG GP9brg6ebroH56QO6LkRfdTQW/jEh7rW1R08NqqrvUz3qdAyiT8M2f3/iXRUbAAUqN8a zYC1Kz8VFCNBHea3NzV94AejE/sG6o9sCN6+uE2b3uyRFHkrRF/ym0PXBFZ4VXpRmtf9 XEAcVxfhX/25YHOEsAzNQ4wPnuTBdN6rkNv0AlPITuCwpaPDeLKpuM6c7kZ7Oy5dL4i2 7mR5KsyGlBE36DrxhZSNGoCgIwMdop9ytcAze8yNMUCeEpqzOCNN+Qlrwo31R+aiZ1PB phBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Nj3vUN1sCuMDZhLchBZ5ljBaRgoXn81VamEs7vmRecg=; b=d9R5TUw8H090O09nzgdRchK3ApexyX6QHRzRAyztZkkujlUi67uxazN1VJtU7I0p3z DrviYKjokMi9AJylz/RND71age/HaHiUrDExrMfISm9AOvhce6Y3aJmCaROhPX4CKNhl Vnp9eOKLbnd2O1ufvsX28utR1F+9vCL9/dm8U4YpWPsadxUUJHU+cFgs1jz6kyYYx+Pm n2dNv3NTV+4yZnOzdBDedrkONZiT9TWWR/C/mng+memxU4XtYdliUsmRLmAaTJRSrk/0 61tP1PZMamtjUvJdu1ftfcbwcZCeFYaZKzOiZwD0Sl4Oj1FPpA6OXJmY4iU61b6u0FqC ajRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Ji3b5vRx; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id l18-20020a5d4812000000b002dbdc70be11sor3282315wrq.54.2023.04.23.10.25.42 for (Google Transport Security); Sun, 23 Apr 2023 10:25:42 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:adf:e803:0:b0:2f7:a333:8cab with SMTP id o3-20020adfe803000000b002f7a3338cabmr8356900wrm.71.1682270742024; Sun, 23 Apr 2023 10:25:42 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([37.159.119.249]) by smtp.gmail.com with ESMTPSA id j32-20020a05600c1c2000b003f173987ec2sm13511653wms.22.2023.04.23.10.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 10:25:41 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/4] ARM: dts: stm32: add CAN support on stm32f746 Date: Sun, 23 Apr 2023 19:25:26 +0200 Message-Id: <20230423172528.1398158-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> References: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Ji3b5vRx; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral configuration and CAN3 in single peripheral configuration: - Dual CAN peripheral configuration: * CAN1: Primary bxCAN for managing the communication between a secondary bxCAN and the 512-byte SRAM memory. * CAN2: Secondary bxCAN with no direct access to the SRAM memory. This means that the two bxCAN cells share the 512-byte SRAM memory and CAN2 can't be used without enabling CAN1. - Single CAN peripheral configuration: * CAN3: Primary bxCAN with dedicated Memory Access Controller unit and 512-byte SRAM memory. ------------------------------------------------------------------------- | features | CAN1 | CAN2 | CAN 3 | ------------------------------------------------------------------------- | SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte | ------------------------------------------------------------------------- | Filters | 26 filters shared between CAN1 & CAN2 | 14 filters | ------------------------------------------------------------------------- Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/stm32f746.dtsi | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index dc868e6da40e..70371d9dbb7a 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -257,6 +257,16 @@ rtc: rtc@40002800 { status = "disabled"; }; + can3: can@40003400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40003400 0x400>; + interrupts = <104>, <105>, <106>, <107>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN3)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; @@ -337,6 +347,35 @@ i2c4: i2c@40006000 { status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan>; + status = "disabled"; + }; + + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + cec: cec@40006c00 { compatible = "st,stm32-cec"; reg = <0x40006C00 0x400>;