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[209.85.220.41]) by mx.google.com with SMTPS id r12-20020a63b10c000000b0053474410e7esor815835pgf.6.2023.06.02.08.27.23 for (Google Transport Security); Fri, 02 Jun 2023 08:27:23 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:6a21:3884:b0:10e:d3a0:cddf with SMTP id yj4-20020a056a21388400b0010ed3a0cddfmr10584617pzb.12.1685719643446; Fri, 02 Jun 2023 08:27:23 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:2003:4e14:c7e6:b770:ced9:e760]) by smtp.gmail.com with ESMTPSA id l3-20020a62be03000000b0063afb08afeesm1154124pff.67.2023.06.02.08.27.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 08:27:22 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: Jonas Karlman , u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , Lukasz Majewski , Sean Anderson Subject: [PATCH 6/7] clk: rockchip: rk3328: Return zero for USB480M clocks Date: Fri, 2 Jun 2023 20:56:30 +0530 Message-Id: <20230602152631.106887-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602152631.106887-1-jagan@amarulasolutions.com> References: <20230602152631.106887-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=kMEJD5XU; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , RK3328 u2phy has assigned-clock-rates on USB480M, return zero for them since the default rates will work fine. Cc: Lukasz Majewski Cc: Sean Anderson Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk_rk3328.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 969b7a8581..0e9b506890 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case ACLK_GMAC: case PCLK_GMAC: case SCLK_USB3OTG_SUSPEND: + case USB480M: return 0; default: return -ENOENT;