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[209.85.220.65]) by mx.google.com with SMTPS id n15-v6sor11700548pfb.30.2018.11.13.03.19.08 for (Google Transport Security); Tue, 13 Nov 2018 03:19:08 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a62:7687:: with SMTP id r129mr2444437pfc.17.1542107948545; Tue, 13 Nov 2018 03:19:08 -0800 (PST) Received: from localhost.localdomain ([2401:4900:3670:3f11:bc71:2ef7:4a39:e260]) by smtp.gmail.com with ESMTPSA id 27-v6sm28531377pfm.36.2018.11.13.03.19.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Nov 2018 03:19:08 -0800 (PST) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Vasily Khoruzhick , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH v4 22/26] clk: sunxi-ng: a64: Add min and max rate for PLL_MIPI Date: Tue, 13 Nov 2018 16:46:29 +0530 Message-Id: <20181113111633.20189-23-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181113111633.20189-1-jagan@amarulasolutions.com> References: <20181113111633.20189-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=bxuNqRYp; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz, but lowering the min rate by 300MHz can result proper working nkms divider with the help of desired dclock rate from panel driver. Signed-off-by: Jagan Teki Acked-by: Stephen Boyd --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 019d67bf97c4..5a3a5b821f8b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -167,6 +167,8 @@ static struct ccu_nkm pll_mipi_clk = { .n = _SUNXI_CCU_MULT(8, 4), .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), .m = _SUNXI_CCU_DIV(0, 4), + .min_rate = 300000000, /* Actual rate is 500MHz */ + .max_rate = 1400000000UL, .common = { .reg = 0x040, .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",