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[62.195.116.103]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a17b01517sm602569366b.157.2024.05.13.07.28.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 May 2024 07:28:18 -0700 (PDT) From: Patrick Barsanti To: linux-amarula@amarulasolutions.com Subject: [PATCH 04/10] arm64: dts: imx8mp-icore-mx8mp-ctouch2-of10: fix ethernet setup Date: Mon, 13 May 2024 16:27:41 +0200 Message-Id: <20240513142747.238064-4-patrick.barsanti@amarulasolutions.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240513142747.238064-1-patrick.barsanti@amarulasolutions.com> References: <20240513142747.238064-1-patrick.barsanti@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: patrick.barsanti@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=C0V8eGol; spf=pass (google.com: domain of patrick.barsanti@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=patrick.barsanti@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Dario Binacchi The patch adds support for reset and other properties to properly drive the PHY. Jira-Id: WAN-971 Upstream-Status: Pending Signed-off-by: Dario Binacchi --- .../imx8mp-icore-mx8mp-ctouch2-of10.dts | 46 +++++++++++-------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts index 4138c4451f0e..3c6ba6693db7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-ctouch2-of10.dts @@ -81,7 +81,9 @@ &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; + phy-mode = "rmii"; + snps,rmii_refclk_ext; + snps,force_thresh_dma_mode; status = "okay"; mdio { @@ -89,10 +91,15 @@ mdio { #address-cells = <1>; #size-cells = <0>; - ethphy0: ethernet-phy@7 { + ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; - micrel,led-mode = <0>; - reg = <7>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0>; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; }; }; }; @@ -179,21 +186,22 @@ &wdog1 { &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 - MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10 + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 + MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x12 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1d0 + MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x1d0 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x1d0 + >; + }; + + pinctrl_ethphy0: ethphy0-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x16 /* Reset */ >; };