[1/4] clk: imx: clk-imx8mn Fix nand and spi clock parent

Message ID 20240707082001.20746-2-michael@amarulasolutions.com
State New
Headers show
Series
  • IMX8 series small clock update
Related show

Commit Message

Michael Nazzareno Trimarchi July 7, 2024, 8:19 a.m. UTC
The osc_24m is the clock-output-name and not the one that
is used as internal name reference from the strcmp. The clock
that use osc_24m, will not be able to reparent it as they should.
We need anyway register the osc_24m clock fixed factor in the clock
tree.

Fixes: 710c4ffb890 ("clk: imx: clk-imx8mn add gpmi nand clocks")
Fixes: 85b1c11989c ("clk: imx: Add ECSPI to iMX8MN")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 drivers/clk/imx/clk-imx8mn.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

Comments

Fabio Estevam July 10, 2024, 1:33 p.m. UTC | #1
Hi Michael,

On Sun, Jul 7, 2024 at 5:20 AM Michael Trimarchi
<michael@amarulasolutions.com> wrote:

> -static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
> +static const char *imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",

The kernel uses osc_24m. Why does U-Boot need to be different?

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Michael Nazzareno Trimarchi July 10, 2024, 1:39 p.m. UTC | #2
Hi

On Wed, Jul 10, 2024 at 3:34 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Michael,
>
> On Sun, Jul 7, 2024 at 5:20 AM Michael Trimarchi
> <michael@amarulasolutions.com> wrote:
>
> > -static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
> > +static const char *imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
>
> The kernel uses osc_24m. Why does U-Boot need to be different?

clk dump

It's how uboot is registering the clk in dts. My idea now was not to
change it to not impact other architectures.
I have a lot of changes but I don't want to address regression and fix
and test before send more patches

MIchael
Fabio Estevam July 10, 2024, 1:43 p.m. UTC | #3
On Wed, Jul 10, 2024 at 10:39 AM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:

> clk dump
>
> It's how uboot is registering the clk in dts. My idea now was not to
> change it to not impact other architectures.
> I have a lot of changes but I don't want to address regression and fix
> and test before send more patches

Ok, I see that 'clock-osc-24m' is already used in U-Boot by the other
peripherals.

Your change looks correct.

Ideally, we should use 'osc_24m' in the future to align with the
kernel, but that's a different task.

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Michael Nazzareno Trimarchi July 11, 2024, 5:56 a.m. UTC | #4
HI Fabio

On Wed, Jul 10, 2024 at 3:43 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Wed, Jul 10, 2024 at 10:39 AM Michael Nazzareno Trimarchi
> <michael@amarulasolutions.com> wrote:
>
> > clk dump
> >
> > It's how uboot is registering the clk in dts. My idea now was not to
> > change it to not impact other architectures.
> > I have a lot of changes but I don't want to address regression and fix
> > and test before send more patches
>
> Ok, I see that 'clock-osc-24m' is already used in U-Boot by the other
> peripherals.
>
> Your change looks correct.
>
> Ideally, we should use 'osc_24m' in the future to align with the
> kernel, but that's a different task.

I will rephrase the commit message

Michael
Fabio Estevam July 22, 2024, 9:07 p.m. UTC | #5
On Thu, Jul 11, 2024 at 2:56 AM Michael Nazzareno Trimarchi
<michael@amarulasolutions.com> wrote:

> I will rephrase the commit message

It looks good as is.

Applied all, thanks.

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Patch

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ed9e16d7c1..bfd1677520 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -57,15 +57,15 @@  static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
 					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
 
 #if CONFIG_IS_ENABLED(DM_SPI)
-static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char *imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 					   "sys_pll2_250m", "audio_pll2_out", };
 
-static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char *imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 					   "sys_pll2_250m", "audio_pll2_out", };
 
-static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
+static const char *imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 					   "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
 					   "sys_pll2_250m", "audio_pll2_out", };
 #endif
@@ -105,7 +105,7 @@  static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
 static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
 					   "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
 
-static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
+static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out",
 						"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
 						"sys_pll2_250m", "video_pll_out", };
 
@@ -119,7 +119,9 @@  static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_10
 
 static int imx8mn_clk_probe(struct udevice *dev)
 {
+	struct clk osc_24m_clk;
 	void __iomem *base;
+	int ret;
 
 	base = (void *)ANATOP_BASE_ADDR;
 
@@ -238,6 +240,11 @@  static int imx8mn_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MN_SYS_PLL2_1000M,
 	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
 
+	ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
+	if (ret)
+		return ret;
+	clk_dm(IMX8MN_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
+
 	base = dev_read_addr_ptr(dev);
 	if (!base)
 		return -EINVAL;