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[93.35.128.17]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a79bc7f1e20sm31483966b.116.2024.07.13.01.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Jul 2024 01:45:45 -0700 (PDT) From: Michael Trimarchi To: Michael Trimarchi Cc: Dario Binacchi , Patrick Barsanti , linux-amarula@amarulasolutions.com Subject: [PATCH 09/21] clk: clk-uclass: Implement CLK_OPS_PARENT_ENABLE Date: Sat, 13 Jul 2024 10:45:14 +0200 Message-ID: <20240713084526.922537-9-michael@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240713084526.922537-1-michael@amarulasolutions.com> References: <20240713084526.922537-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=rG3P8a00; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , There are scenario that we need to enable the new parent clock before reparent, or we need to do the same with clk_set_rate. The patch cover those scenario Signed-off-by: Michael Trimarchi --- drivers/clk/clk-uclass.c | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 76f1026164..8faf5a56e1 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -583,7 +583,9 @@ static void clk_clean_rate_cache(struct clk *clk) ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; + struct clk *pclk; struct clk *clkp; + ulong ret; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); if (!clk_valid(clk)) @@ -598,11 +600,37 @@ ulong clk_set_rate(struct clk *clk, ulong rate) /* Clean up cached rates for us and all child clocks */ clk_clean_rate_cache(clkp); - return ops->set_rate(clk, rate); + if (clk->flags & CLK_SET_RATE_UNGATE) { + ret = clk_enable(clk); + if (ret) + return ret; + } + + pclk = clk_get_parent(clk); + if (pclk) { + if (clk->flags & CLK_OPS_PARENT_ENABLE) { + ret = clk_enable(pclk); + if (ret) + goto out; + } + } + + ret = ops->set_rate(clk, rate); + + if (pclk && clk->flags & CLK_OPS_PARENT_ENABLE) + clk_disable(pclk); + +out: + if (clk->flags & CLK_SET_RATE_UNGATE) + clk_disable(clk); + + return ret; } int clk_set_parent(struct clk *clk, struct clk *parent) { + struct clk *old_parent; + const struct clk_ops *ops; int ret; @@ -614,6 +642,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent) if (!ops->set_parent) return -ENOSYS; + if (clk->enable_count) + clk_enable(parent); + + old_parent = clk_get_parent(clk); + if (clk->flags & CLK_OPS_PARENT_ENABLE) { + clk_enable(old_parent); + clk_enable(parent); + } + ret = ops->set_parent(clk, parent); if (ret) return ret; @@ -621,6 +658,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent) if (CONFIG_IS_ENABLED(CLK_CCF)) ret = device_reparent(clk->dev, parent->dev); + if (clk->flags & CLK_OPS_PARENT_ENABLE) { + clk_disable(parent); + clk_disable(old_parent); + } + + if (clk->enable_count) + clk_disable(old_parent); + return ret; }