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[5.91.58.211]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-59b25528dc1sm1929469a12.52.2024.07.14.04.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jul 2024 04:33:15 -0700 (PDT) From: Michael Trimarchi To: Michael Trimarchi Cc: Dario Binacchi , Patrick Barsanti , linux-amarula@amarulasolutions.com Subject: [PATCH 10/25] clk: imx8mm: Mark IMX8MM_SYS_PLL2 and IMX8MM_SYS_PLL3 as enabled Date: Sun, 14 Jul 2024 13:32:47 +0200 Message-ID: <20240714113302.133399-10-michael@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240714113302.133399-1-michael@amarulasolutions.com> References: <20240714113302.133399-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=k3XeHeFQ; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Both clock are enabled by the bootloader and we need to increase their reference count to avoid disable during reparent operation. Signed-off-by: Michael Trimarchi --- drivers/clk/imx/clk-imx8mm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 685e7df0e5..275f119686 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -170,6 +170,8 @@ static const char * const imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200 static int imx8mm_clk_probe(struct udevice *dev) { void __iomem *base; + struct clk *clk; + int ret; base = (void *)ANATOP_BASE_ADDR; @@ -448,6 +450,13 @@ static int imx8mm_clk_probe(struct udevice *dev) clk_dm(IMX8MM_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0)); #endif + ret = clk_get_by_id(IMX8MM_SYS_PLL2, &clk); + if (!ret) + clk_enable(clk); + + ret = clk_get_by_id(IMX8MM_SYS_PLL3, &clk); + if (!ret) + clk_enable(clk); return 0; }