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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-42caf2c53absor37552555e9.7.2024.09.11.08.10.42 for (Google Transport Security); Wed, 11 Sep 2024 08:10:42 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:600c:4f88:b0:426:62c5:4741 with SMTP id 5b1f17b1804b1-42cae70a06bmr108872065e9.2.1726067441870; Wed, 11 Sep 2024 08:10:41 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com ([2.196.41.3]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42cb116f44esm137688375e9.45.2024.09.11.08.10.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 08:10:41 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Subject: [PATCH v2 02/27] clk: imx8mn: Prevent clock critical path from disabling during reparent and set_rate Date: Wed, 11 Sep 2024 17:10:14 +0200 Message-ID: <20240911151039.2914886-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911151039.2914886-1-dario.binacchi@amarulasolutions.com> References: <20240911151039.2914886-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=f8T7N9iW; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi This commit ensures that critical clock paths are not disabled during reparent and set_rate operations within the clock framework, paving the way for the inclusion of new features. Signed-off-by: Michael Trimarchi --- drivers/clk/imx/clk-imx8mn.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 8911e342f18b..e089012477a6 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -27,10 +27,18 @@ static const char * const imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", " "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll_out", "audio_pll2_out", }; + static const char * const imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", }; +static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", + "video_pll_out", "sys_pll1_100m",}; + static const char * const imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", }; @@ -65,6 +73,9 @@ static const char * const imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; +static const char * const imx8mn_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll1_800m", "clk_ext2", + "clk_ext4", "audio_pll2_out" }; #if CONFIG_IS_ENABLED(DM_SPI) static const char * const imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", @@ -284,15 +295,18 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1)); + /* BUS */ + clk_dm(IMX8MN_CLK_MAIN_AXI, + imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800)); clk_dm(IMX8MN_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, - base + 0x8880)); + imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MN_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", - imx8mn_nand_usdhc_sels, + imx8m_clk_composite_critical("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900)); clk_dm(IMX8MN_CLK_USB_BUS, imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80)); + clk_dm(IMX8MN_CLK_NOC, + imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00)); /* IP */ clk_dm(IMX8MN_CLK_USDHC1, @@ -387,7 +401,8 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif - + clk_dm(IMX8MN_CLK_GIC, + imx8m_clk_composite_critical("gic", imx8mn_gic_sels, base + 0xb200)); #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MN_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));