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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-42caf301b44sor47406835e9.10.2024.09.11.08.16.06 for (Google Transport Security); Wed, 11 Sep 2024 08:16:06 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a05:600c:524c:b0:42c:b555:43dd with SMTP id 5b1f17b1804b1-42cb55545fdmr117431555e9.3.1726067765966; Wed, 11 Sep 2024 08:16:05 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com ([2.196.41.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378956d37a1sm11797177f8f.77.2024.09.11.08.16.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2024 08:16:05 -0700 (PDT) From: Dario Binacchi To: linux-amarula@amarulasolutions.com Subject: [PATCH v2 10/10] drm/mxsfb: stop controller and drain FIFOs if already initialized Date: Wed, 11 Sep 2024 17:15:55 +0200 Message-ID: <20240911151555.2915258-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240911151555.2915258-1-dario.binacchi@amarulasolutions.com> References: <20240911151555.2915258-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=JkhSBbVa; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , You can't re-program the controller if it is still running. This may lead to shifted pictures (FIFO issue?), so stop the controller and drain its FIFOs in case it's already properly setup. This patch is crucial when supporting the simple framebuffer, as the controller has already been initialized by the bootloader. Signed-off-by: Dario Binacchi --- drivers/gpu/drm/mxsfb/mxsfb_drv.c | 3 +++ drivers/gpu/drm/mxsfb/mxsfb_drv.h | 1 + drivers/gpu/drm/mxsfb/mxsfb_kms.c | 14 +++++++++++++- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index a8d6dffcd02c..563e308912aa 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -222,6 +223,8 @@ static int mxsfb_load(struct drm_device *drm, if (!mxsfb) return -ENOMEM; + mxsfb->enabled = + of_property_read_bool(drm->dev->of_node, "fsl,boot-on"); mxsfb->drm = drm; drm->dev_private = mxsfb; mxsfb->devdata = devdata; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h index d160d921b25f..0f9ae4ce450c 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h @@ -47,6 +47,7 @@ struct mxsfb_drm_private { struct drm_bridge *bridge; bool crc_active; + bool enabled; }; static inline struct mxsfb_drm_private * diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c index 7ed2516b6de0..d064a2bb65df 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c @@ -202,9 +202,11 @@ static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb) writel(reg, mxsfb->base + LCDC_CTRL1); writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET); + + mxsfb->enabled = true; } -static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) +static void _mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) { u32 reg; @@ -221,6 +223,13 @@ static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) reg &= ~VDCTRL4_SYNC_SIGNALS_ON; writel(reg, mxsfb->base + LCDC_VDCTRL4); + mxsfb->enabled = false; +} + +static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb) +{ + _mxsfb_disable_controller(mxsfb); + clk_disable_unprepare(mxsfb->clk); if (mxsfb->clk_disp_axi) clk_disable_unprepare(mxsfb->clk_disp_axi); @@ -354,6 +363,9 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, u32 bus_format = 0; dma_addr_t dma_addr; + if (mxsfb->enabled) + _mxsfb_disable_controller(mxsfb); + pm_runtime_get_sync(drm->dev); mxsfb_enable_axi_clk(mxsfb);