From patchwork Wed Nov 6 08:57:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 3623 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f71.google.com (mail-ed1-f71.google.com [209.85.208.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 264883F14C for ; Wed, 6 Nov 2024 10:06:14 +0100 (CET) Received: by mail-ed1-f71.google.com with SMTP id 4fb4d7f45d1cf-5cd50bf580csf4840740a12.0 for ; Wed, 06 Nov 2024 01:06:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1730883974; cv=pass; d=google.com; s=arc-20240605; b=h9T+p8NU7FWGxKuyVGGSdQTuWDBOTjTEzVXYtOaWeL/CXW3z3P1wrQVxdrd0j4x9t8 CT0B+pqwo03ohyZNPDYnPktalhiVclOA4gbNW7e6rsjwu6NrFDn2NEOu+70ki+IfqnNQ OEe15VpN55eUHBiBtkZTr3j8i5dsXBz/R0PWBOIU22C6TIU24Jwk+Gsz/P/Brp9pvZwN NUU4UDNE4QGPFT+13qDJevjXt17dGe/WBT1eGXxKdwS8A5ozsWBoam8q/lLOvv4PZgDm 8YsieJZsH2dFk5QnvxyLdFIKspAqRnLHu7n4aRvNTJpcfc0Vwbo7cjul+lXFe+s75NcV eCHA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hDpHbkpfdx4gXd1JCeuNz3EmiSCdKkWZGM7BYT+VG9o=; fh=wIqwhvTUiLEB//xDMlIj7Y1ZB8NirH6YUloIpp4wltE=; b=O1aKHnC/jPnByGzntUSvFbV5NDwA80prpFYcaZr87E5EompQOiMn4xuHjfzgFaV6Vs yDyYZPmOIHqPZJG5lZCIH4+wOs5lgXqZshIkgGUpQNwltYU7Q+YnqtaXQRMXkJ0oj57a oqnlb5NOD4SYPfJrPY/RzQMnLTvukMKaSsdYSx+VjSYOCG3N2Wdy+iSmXmwNqqYgxErZ 4vLUG8Wj3sLqbrHPCMTxmGnQL0bpKb9wWm7+o+I+MiG4s2lTJaIhl1CBZ9jbfH2/HVdc gnq4JveNFPcjHQyazYOkX05HZf258zIkm7LH17nY3bXzLPz7N2HGa5cjIcOro3rrh6aD na6Q==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZpR0GtVE; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1730883974; x=1731488774; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=hDpHbkpfdx4gXd1JCeuNz3EmiSCdKkWZGM7BYT+VG9o=; b=iLkS0jKigdPrOgg2kwCdZ5dgU2Y/4RfMmWTBDwUBQ97qKg+Q/1qourwgtEyWJ4803D vcyhv6gvonNzbbJi3PZFK89o589gjHpbAXIC0y56SGAxsvtMaZQejouq25OL7SaUyDzY gAMMdITEK4APqCjXyDT54CWgRjLNGzF2Jrxlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1730883974; x=1731488774; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=hDpHbkpfdx4gXd1JCeuNz3EmiSCdKkWZGM7BYT+VG9o=; b=KmSAnnV+x07Qw437xz1Lrnrj9Fh7lpYSZNsdF53bYc5WrX8u06a12sutVJT9txEDIC +IX9E8kyttFaI+ZnxLxKRLqZDL/+taFLszon643ewNUB5DzT4mMK8B4y0BPKDyHYwnkR 6j1ZwHdkVxUrBXjQaph7X24uTXUvjjfXHhc1X5HtUoxFJ5XYHX0KVBXSFx013qpV5AQ9 6pO1E78sG33s8xerXg5Ixy/xMd7QSpqrPNdTRvL3bIhYbkr5Pzlr4aK6/AfFxNAq+iJj UygVnualMqEY9dDCR1q+qAfGe9BUF6WQG7tqnwjzuC2oKTh6yuids7tYzn0N4vND5B3x bHbA== X-Forwarded-Encrypted: i=2; AJvYcCXMFu+Yo11OQH2N3QJMx8ApvRxYzqjSTwprsiWyaU4ExQ5r98YBWP2uzzM2v0l2YGj1Hkoh6FJz4CjUL5dA@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YwuWUq9UNTim1Z+OfJpBsww6H+Uaf+4+4pZNnJRhiORIdJ1kRcz SJaSoQ1WxzOogu/vFULvw6mboj7FfP75H7LWXIcg681bUHZrScGSoKI5zYw+TrWHng== X-Google-Smtp-Source: AGHT+IEE5kPnzttnV0mhvbUU176GWwkdyO7iIQqZF1v7nqRfKz+7BZ3SRM8LHtz8gCDvpkU+xS24EQ== X-Received: by 2002:a05:6402:180f:b0:5ce:afba:f48e with SMTP id 4fb4d7f45d1cf-5ceb9383c22mr11461871a12.32.1730883973433; Wed, 06 Nov 2024 01:06:13 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:aa7:c143:0:b0:5ce:c9e0:aeb2 with SMTP id 4fb4d7f45d1cf-5cec9e0b1a0ls805839a12.1.-pod-prod-04-eu; Wed, 06 Nov 2024 01:06:11 -0800 (PST) X-Received: by 2002:a17:907:2684:b0:a99:543e:94b4 with SMTP id a640c23a62f3a-a9e658be221mr1913741166b.56.1730883971450; Wed, 06 Nov 2024 01:06:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1730883971; cv=none; d=google.com; s=arc-20240605; b=ixsSaGTvy0NBAx9j8spfMUrkPQJ3mccDM0EAZSZxyau5XLFvG5/loGwyyjZi9fuT1t yEPsOFhnDLX2WYZsXyB5Urq7Jitrqt6VWGRYFv/23Ug8pzQR0pOmZKcicke5Z24DVRvm 5ZWrOaLripKz1BPcPz+QXPqySogxM5lRLcG52zGzu0CRAcMF52FeOFaRKLmARANvUa8X 8ujgvd9QDRaaYDBmP2AFoNuhMZiwcLTYKqlDssDGiLqcKkkn8KwtIdfOzMY50LGeFLB6 EppF/GJ35vVE5BjChHK45an5ZfkKkMYsSreEkdZxdXT0aiRTXGicOPdnDezx0BGuX36x 0N0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HYFE+8+xJyXnOIazKfuEkYOBmIG07KamRjf0rhIE9ik=; fh=u/u80m6tBSaxW7VWG5AQatIbYzkIAnRGhZp/RTASK5o=; b=TKnBRwNcGMRdwwcXFOU+zGoJu/2qyXFtDFtWVamntoPeecQsnm0PNPf3LrXrd+K0QV NXFpEXToCefG+I850mfeo0EmCjQK2JJd/4spm+kXnmN86parA4uiSI3OX0nalVdIcwPW h3N+rTJBYEKO2dS9mn7aycBFMSQvB2ugvaazbgGMBv85NiBhDr875uu9BbKyEcEbc1vU 16yRdxv4zhZUR/Cj6WLdNWpErU1rtzqo+o3MGqman56MZ/AiedY+jeCyg45/6DcRmme1 G6Z20/q8fIuuR2ijLlobgfzxmIIZ2G33v/7DpNs4k63ZfNnXdo4lhiakL8pSe0nkCcfx G/HA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZpR0GtVE; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-a9e564b97e7sor606585766b.8.2024.11.06.01.06.11 for (Google Transport Security); Wed, 06 Nov 2024 01:06:11 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Received: by 2002:a17:907:3f05:b0:a99:375f:4523 with SMTP id a640c23a62f3a-a9e6587e27dmr1945150966b.44.1730883970924; Wed, 06 Nov 2024 01:06:10 -0800 (PST) Received: from localhost.localdomain ([2001:b07:6474:ebbf:afb5:f524:6416:8e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9eb17f9422sm247781366b.139.2024.11.06.01.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Nov 2024 01:06:10 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v3 2/8] clk: imx: pll14xx: support spread spectrum clock generation Date: Wed, 6 Nov 2024 09:57:58 +0100 Message-ID: <20241106090549.3684963-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> References: <20241106090549.3684963-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ZpR0GtVE; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds support for spread spectrum clock (SSC) generation for the pll14xxx. The addition of the "imx_clk_hw_pll14xx_ssc" macro has minimized the number of changes required to avoid compilation errors following the addition of the SSC setup parameter to the "imx_dev_clk_hw_pll14xx" macro used in the files clk-imx8m{m,n,p}.c. The change to the clk-imx8mp-audiomix.c file prevents the patch from causing a compilation error. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-imx8mp-audiomix.c | 2 +- drivers/clk/imx/clk-pll14xx.c | 102 +++++++++++++++++++++++++- drivers/clk/imx/clk.h | 24 +++++- 3 files changed, 124 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp-audiomix.c b/drivers/clk/imx/clk-imx8mp-audiomix.c index b2cb157703c5..bfcf2975c217 100644 --- a/drivers/clk/imx/clk-imx8mp-audiomix.c +++ b/drivers/clk/imx/clk-imx8mp-audiomix.c @@ -365,7 +365,7 @@ static int clk_imx8mp_audiomix_probe(struct platform_device *pdev) clk_hw_data->hws[IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL] = hw; hw = imx_dev_clk_hw_pll14xx(dev, "sai_pll", "sai_pll_ref_sel", - base + 0x400, &imx_1443x_pll); + base + 0x400, &imx_1443x_pll, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto err_clk_register; diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..76014e243a57 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) #define LOCK_TIMEOUT_US 10000 @@ -40,6 +46,7 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + struct imx_pll14xx_ssc ssc; }; #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +354,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static void clk_pll1443x_set_sscg(struct clk_hw *hw, unsigned long parent_rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *ssc = &pll->ssc; + u32 sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL); + + sscg_ctrl &= + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + if (ssc->enable) { + u32 mfr = parent_rate / (ssc->mod_freq * pdiv * (1 << 5)); + u32 mrr = (ssc->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, ssc->mod_type); + } + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +396,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } @@ -408,6 +439,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, gnrl_ctl &= ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + if (pll->ssc.enable) + clk_pll1443x_set_sscg(hw, prate, rate.pdiv, rate.mdiv); + return 0; } @@ -487,7 +521,8 @@ static const struct clk_ops clk_pll1443x_ops = { struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk) + const struct imx_pll14xx_clk *pll_clk, + const struct imx_pll14xx_ssc *ssc) { struct clk_pll14xx *pll; struct clk_hw *hw; @@ -525,6 +560,8 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, pll->type = pll_clk->type; pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; + if (ssc) + memcpy(&pll->ssc, ssc, sizeof(pll->ssc)); val = readl_relaxed(pll->base + GNRL_CTL); val &= ~BYPASS_MASK; @@ -542,3 +579,66 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +static enum imx_pll14xx_ssc_mod_type clk_pll14xx_ssc_mode(const char *name, + enum imx_pll14xx_ssc_mod_type def) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_methods[] = { + { .name = "down-spread", .id = IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name = "up-spread", .id = IMX_PLL14XX_SSC_UP_SPREAD }, + { .name = "center-spread", .id = IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + for (i = 0; i < ARRAY_SIZE(mod_methods); i++) { + if (!strcmp(name, mod_methods[i].name)) + return mod_methods[i].id; + } + + return def; +} + +void imx_clk_pll14xx_get_ssc_conf(struct device_node *np, int pll_id, + struct imx_pll14xx_ssc *ssc) +{ + int i, ret, offset, num_clks; + u32 clk_id, clk_cell_size; + const char *s; + + if (!ssc) + return; + + memset(ssc, 0, sizeof(*ssc)); + + num_clks = of_count_phandle_with_args(np, "fsl,ssc-clocks", + "#clock-cells"); + if (num_clks <= 0) + return; + + ret = of_property_read_u32(np, "#clock-cells", &clk_cell_size); + if (ret) + return; + + for (i = 0; i < num_clks; i++) { + offset = i * clk_cell_size + 1; + of_property_read_u32_index(np, "fsl,ssc-clocks", offset, + &clk_id); + if (clk_id != pll_id) + continue; + + of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", i, + &ssc->mod_freq); + of_property_read_u32_index(np, "fsl,ssc-modrate-percent", i, + &ssc->mod_rate); + if (!of_property_read_string(np, "fsl,ssc-modmethod", &s)) + ssc->mod_type = clk_pll14xx_ssc_mode( + s, IMX_PLL14XX_SSC_DOWN_SPREAD); + + ssc->enable = true; + break; + } +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_get_ssc_conf); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..8cbc75480569 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -62,6 +62,19 @@ struct imx_pll14xx_rate_table { unsigned int kdiv; }; +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + bool enable; + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + struct imx_pll14xx_clk { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; @@ -222,11 +235,18 @@ extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer; __imx_clk_hw_divider(name, parent, reg, shift, width, flags) #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ - imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk) + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, NULL) + +#define imx_clk_hw_pll14xx_ssc(name, parent_name, base, pll_clk, ssc) \ + imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk, ssc) struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, - const struct imx_pll14xx_clk *pll_clk); + const struct imx_pll14xx_clk *pll_clk, + const struct imx_pll14xx_ssc *ssc); + +void imx_clk_pll14xx_get_ssc_conf(struct device_node *np, int pll_id, + struct imx_pll14xx_ssc *ssc); struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, const char *parent, void __iomem *base);