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[209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-aa625e4b5b1sor59225966b.4.2024.12.05.03.20.10 for (Google Transport Security); Thu, 05 Dec 2024 03:20:10 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncslSbQYEU3yHe+y0/R9tWgZa76TcHnUpLDyePjqo/PpLBJGFHLciSKQeMy32Zw 6MtCAb21IxPqxiBk4v4KASKLRYoifKFMl5qQ9M+GGQGL+HUIUpxkR5mfys/X4d0Fgf8eWhBiPOw jstU7JSTsMCvWihRXd3dR3PFKjJxd0VbaB9az+aZp7d9jUjguvFMR+TGyWyRFarlyO0DWwow7Il lXH7Y5DmwiglSkMoHl6Phf8QrMpPhRO36DEV+O1rKGLBQe0eZp0tqdHXS84HQUpt9XqtAiBBybB g1q7iL5Snz1vg84M3RDR7vU9LMgr7q4iwkBsSux4CQJ7Rg== X-Received: by 2002:a17:907:3a57:b0:aa6:2cfc:3157 with SMTP id a640c23a62f3a-aa62cfc4dffmr74669566b.33.1733397610192; Thu, 05 Dec 2024 03:20:10 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com ([2001:b07:6474:ebbf:61a1:9bc8:52c6:3c2d]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa625eedcd0sm77505266b.87.2024.12.05.03.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 03:20:09 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v5 19/20] clk: imx: pll14xx: support spread spectrum clock generation Date: Thu, 5 Dec 2024 12:17:54 +0100 Message-ID: <20241205111939.1796244-20-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241205111939.1796244-1-dario.binacchi@amarulasolutions.com> References: <20241205111939.1796244-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=jrYZ8ESJ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for spread spectrum clock (SSC) generation to the pll14xxx driver. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/clk/imx/clk-pll14xx.c | 126 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 16 +++++ 2 files changed, 142 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12c..1e66c3bb230d 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -20,6 +20,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -31,6 +33,10 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_MASK GENMASK(1, 0) #define LOCK_TIMEOUT_US 10000 @@ -40,6 +46,8 @@ struct clk_pll14xx { enum imx_pll14xx_type type; const struct imx_pll14xx_rate_table *rate_table; int rate_count; + bool ssc_enable; + struct imx_pll14xx_ssc ssc_conf; }; #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -347,6 +355,27 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static void clk_pll1443x_enable_ssc(struct clk_hw *hw, unsigned long parent_rate, + unsigned int pdiv, unsigned int mdiv) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct imx_pll14xx_ssc *conf = &pll->ssc_conf; + u32 sscg_ctrl, mfr, mrr; + + sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &= + ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + mfr = parent_rate / (conf->mod_freq * pdiv * (1 << 5)); + mrr = (conf->mod_rate * mdiv * (1 << 6)) / (100 * mfr); + + sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, conf->mod_type); + + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -368,6 +397,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } @@ -408,6 +440,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, gnrl_ctl &= ~BYPASS_MASK; writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL); + if (pll->ssc_enable) + clk_pll1443x_enable_ssc(hw, prate, rate.pdiv, rate.mdiv); + return 0; } @@ -542,3 +577,94 @@ struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, return hw; } EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx); + +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + + pll->ssc_enable = true; + memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf)); +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_enable_ssc); + +static int clk_pll14xx_ssc_mod_type(const char *name, + enum imx_pll14xx_ssc_mod_type *mod_type) +{ + int i; + struct { + const char *name; + enum imx_pll14xx_ssc_mod_type id; + } mod_types[] = { + { .name = "down-spread", .id = IMX_PLL14XX_SSC_DOWN_SPREAD }, + { .name = "up-spread", .id = IMX_PLL14XX_SSC_UP_SPREAD }, + { .name = "center-spread", .id = IMX_PLL14XX_SSC_CENTER_SPREAD } + }; + + pr_info("%s, name: %s\n", __func__, name); + for (i = 0; i < ARRAY_SIZE(mod_types); i++) { + if (!strcmp(name, mod_types[i].name)) { + *mod_type = mod_types[i].id; + return 0; + } + } + + return -EINVAL; +} + +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name, + struct imx_pll14xx_ssc *conf) +{ + int i, ret, num_clks; + const char *s; + + if (!conf) + return -EINVAL; + + ret = of_property_count_strings(np, "clock-names"); + if (ret < 0) + return ret; + + num_clks = ret; + for (i = 0; i < num_clks; i++) { + ret = of_property_read_string_index(np, "clock-names", i, &s); + if (strcmp(pll_name, s)) + continue; + + ret = of_property_read_u32_index(np, "fsl,ssc-modfreq-hz", i, + &conf->mod_freq); + if (ret) + return ret; + + ret = of_property_read_u32_index(np, "fsl,ssc-modrate-percent", i, + &conf->mod_rate); + if (ret) { + pr_err("missing fsl,ssc-modrate-percent property for %pOFn\n", + np); + return ret; + } + + ret = of_property_read_string_index(np, "fsl,ssc-modmethod", i, &s); + if (ret) { + pr_err("failed to get fsl,ssc-modmethod property for %pOFn\n", + np); + return ret; + } + + if (strlen(s) == 0) + return -ENODEV; + + ret = clk_pll14xx_ssc_mod_type(s, &conf->mod_type); + if (ret) { + pr_err("wrong fsl,ssc-modmethod property for %pOFn\n", np); + return ret; + } + + pr_debug("%s: mod_freq: %d, mod_rate: %d: mod_method: %s [%d]\n", + __func__, conf->mod_freq, conf->mod_rate, s, conf->mod_type); + + return 0; + } + + return -ENODEV; +} +EXPORT_SYMBOL_GPL(imx_clk_pll14xx_ssc_parse_dt); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 52055fda3058..edd28b78b115 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -69,6 +69,18 @@ struct imx_pll14xx_clk { int flags; }; +enum imx_pll14xx_ssc_mod_type { + IMX_PLL14XX_SSC_DOWN_SPREAD, + IMX_PLL14XX_SSC_UP_SPREAD, + IMX_PLL14XX_SSC_CENTER_SPREAD, +}; + +struct imx_pll14xx_ssc { + unsigned int mod_freq; + unsigned int mod_rate; + enum imx_pll14xx_ssc_mod_type mod_type; +}; + extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; @@ -494,4 +506,8 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, struct clk_hw *imx8m_anatop_get_clk_hw(int id); #endif +void imx_clk_pll14xx_enable_ssc(struct clk_hw *hw, struct imx_pll14xx_ssc *conf); +int imx_clk_pll14xx_ssc_parse_dt(struct device_node *np, const char *pll_name, + struct imx_pll14xx_ssc *conf); + #endif