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[209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-aac0e841a7fsor262256866b.6.2024.12.22.09.05.55 for (Google Transport Security); Sun, 22 Dec 2024 09:05:56 -0800 (PST) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGnctWwotlTwFszG8rh8dlU8Z9ONpqywB+eeJ6FwmYIOvlUa8+xtJ2ITJDklvDp33 /ssmcybJc6K9kXDkPxLBFI+Q+5ha3FTy95pWVK8w0g2pI/bEsvumCCQVY9hknmNQRr4ueWZ4uW6 65YbCjhwRT37JQ/pg7kRMW7xubWp8oS7rGKJ+ZcOPd2faUDl3xkrEUllV6IA4ONxAvdv3phKCd/ 1s2wBmaa7TESdlOYVa2vLZYdNV0ukxUVewwkG5Ot4hXWJbj2XfO2sgexN4sC5CPrdDIZWQMjR5g IL28IVHxmLRfPftDkezwip6vV5K6eDZsTzGPhFvNz6uWUQ== X-Received: by 2002:a05:6402:51c8:b0:5d3:cd5b:64a9 with SMTP id 4fb4d7f45d1cf-5d81de39872mr7776824a12.34.1734887155565; Sun, 22 Dec 2024 09:05:55 -0800 (PST) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com ([2.196.41.87]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aac0efe48d6sm414056566b.127.2024.12.22.09.05.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Dec 2024 09:05:55 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Fabio Estevam , Michael Turquette , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v6 10/18] clk: imx: add hw API imx8m_anatop_get_clk_hw Date: Sun, 22 Dec 2024 18:04:25 +0100 Message-ID: <20241222170534.3621453-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241222170534.3621453-1-dario.binacchi@amarulasolutions.com> References: <20241222170534.3621453-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=WgpODsqg; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Get the hw of a clock registered by the anatop module. This function is preparatory for future developments. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Consider CONFIG_CLK_IMX8M{M,N,P,Q}_MODULE to fix compilation errors Changes in v4: - New drivers/clk/imx/clk.c | 28 ++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 7 +++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c index df83bd939492..9a21f233e105 100644 --- a/drivers/clk/imx/clk.c +++ b/drivers/clk/imx/clk.c @@ -128,6 +128,34 @@ struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name) } EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name); +#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MM_MODULE) || \ + defined(CONFIG_CLK_IMX8MN) || defined(CONFIG_CLK_IMX8MN_MODULE) || \ + defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MP_MODULE) || \ + defined(CONFIG_CLK_IMX8MQ) || defined(CONFIG_CLK_IMX8MQ_MODULE) +struct clk_hw *imx8m_anatop_get_clk_hw(int id) +{ +#if defined(CONFIG_CLK_IMX8MQ) || defined(CONFIG_CLK_IMX8MQ_MODULE) + const char *compatible = "fsl,imx8mq-anatop"; +#else + const char *compatible = "fsl,imx8mm-anatop"; +#endif + struct device_node *np; + struct of_phandle_args args; + struct clk_hw *hw; + + np = of_find_compatible_node(NULL, NULL, compatible); + args.np = np; + args.args_count = 1; + args.args[0] = id; + of_node_put(np); + + hw = __clk_get_hw(of_clk_get_from_provider(&args)); + pr_debug("%s: got clk: %s\n", __func__, clk_hw_get_name(hw)); + return hw; +} +EXPORT_SYMBOL_GPL(imx8m_anatop_get_clk_hw); +#endif + /* * This fixups the register CCM_CSCMR1 write value. * The write/read/divider values of the aclk_podf field diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index aa5202f284f3..52055fda3058 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -487,4 +487,11 @@ struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask); +#if defined(CONFIG_CLK_IMX8MM) || defined(CONFIG_CLK_IMX8MM_MODULE) || \ + defined(CONFIG_CLK_IMX8MN) || defined(CONFIG_CLK_IMX8MN_MODULE) || \ + defined(CONFIG_CLK_IMX8MP) || defined(CONFIG_CLK_IMX8MP_MODULE) || \ + defined(CONFIG_CLK_IMX8MQ) || defined(CONFIG_CLK_IMX8MQ_MODULE) +struct clk_hw *imx8m_anatop_get_clk_hw(int id); +#endif + #endif