diff --git a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml index bbd22e95b319..f439b0a94ce2 100644 --- a/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml +++ b/Documentation/devicetree/bindings/clock/fsl,imx8m-anatop.yaml @@ -30,22 +30,73 @@ properties: interrupts: maxItems: 1 + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + '#clock-cells': const: 1 required: - compatible - reg + - clocks + - clock-names - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8mq-anatop + then: + properties: + clocks: + items: + - description: 32k osc + - description: 25m osc + - description: 27m osc + clock-names: + items: + - const: ckil + - const: osc_25m + - const: osc_27m + else: + properties: + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: osc_32k + - const: osc_24m + additionalProperties: false examples: - | - anatop: clock-controller@30360000 { + clock-controller@30360000 { compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>; + clock-names = "osc_32k", "osc_24m"; + }; + + - | + clock-controller@30360000 { + compatible = "fsl,imx8mq-anatop"; + reg = <0x30360000 0x10000>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc_25m>, <&osc_27m>; + clock-names = "ckil", "osc_25m", "osc_27m"; }; ... diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 102d8a6cdb55..017c06e48430 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -287,4 +287,68 @@ #define IMX8MM_CLK_END 258 +#define IMX8MM_ANATOP_CLK_DUMMY 0 +#define IMX8MM_ANATOP_CLK_32K 1 +#define IMX8MM_ANATOP_CLK_24M 2 +#define IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MM_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MM_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MM_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MM_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MM_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MM_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MM_ANATOP_AUDIO_PLL1 11 +#define IMX8MM_ANATOP_AUDIO_PLL2 12 +#define IMX8MM_ANATOP_VIDEO_PLL 13 +#define IMX8MM_ANATOP_DRAM_PLL 14 +#define IMX8MM_ANATOP_GPU_PLL 15 +#define IMX8MM_ANATOP_VPU_PLL 16 +#define IMX8MM_ANATOP_ARM_PLL 17 +#define IMX8MM_ANATOP_SYS_PLL1 18 +#define IMX8MM_ANATOP_SYS_PLL2 19 +#define IMX8MM_ANATOP_SYS_PLL3 20 +#define IMX8MM_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MM_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MM_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MM_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MM_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MM_ANATOP_VPU_PLL_BYPASS 26 +#define IMX8MM_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MM_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MM_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MM_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MM_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MM_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MM_ANATOP_GPU_PLL_OUT 33 +#define IMX8MM_ANATOP_VPU_PLL_OUT 34 +#define IMX8MM_ANATOP_ARM_PLL_OUT 35 +#define IMX8MM_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MM_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MM_ANATOP_SYS_PLL1_40M 38 +#define IMX8MM_ANATOP_SYS_PLL1_80M 39 +#define IMX8MM_ANATOP_SYS_PLL1_100M 40 +#define IMX8MM_ANATOP_SYS_PLL1_133M 41 +#define IMX8MM_ANATOP_SYS_PLL1_160M 42 +#define IMX8MM_ANATOP_SYS_PLL1_200M 43 +#define IMX8MM_ANATOP_SYS_PLL1_266M 44 +#define IMX8MM_ANATOP_SYS_PLL1_400M 45 +#define IMX8MM_ANATOP_SYS_PLL1_800M 46 +#define IMX8MM_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MM_ANATOP_SYS_PLL2_50M 48 +#define IMX8MM_ANATOP_SYS_PLL2_100M 49 +#define IMX8MM_ANATOP_SYS_PLL2_125M 50 +#define IMX8MM_ANATOP_SYS_PLL2_166M 51 +#define IMX8MM_ANATOP_SYS_PLL2_200M 52 +#define IMX8MM_ANATOP_SYS_PLL2_250M 53 +#define IMX8MM_ANATOP_SYS_PLL2_333M 54 +#define IMX8MM_ANATOP_SYS_PLL2_500M 55 +#define IMX8MM_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MM_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MM_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MM_ANATOP_CLK_CLKOUT1 59 +#define IMX8MM_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MM_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MM_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mn-clock.h b/include/dt-bindings/clock/imx8mn-clock.h index 04809edab33c..b2fa73803d45 100644 --- a/include/dt-bindings/clock/imx8mn-clock.h +++ b/include/dt-bindings/clock/imx8mn-clock.h @@ -267,4 +267,68 @@ #define IMX8MN_CLK_END 235 +#define IMX8MN_ANATOP_CLK_DUMMY 0 +#define IMX8MN_ANATOP_CLK_32K 1 +#define IMX8MN_ANATOP_CLK_24M 2 +#define IMX8MN_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MN_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MN_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MN_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MN_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MN_ANATOP_M7_ALT_PLL_REF_SEL 8 +#define IMX8MN_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MN_ANATOP_SYS_PLL3_REF_SEL 10 +#define IMX8MN_ANATOP_AUDIO_PLL1 11 +#define IMX8MN_ANATOP_AUDIO_PLL2 12 +#define IMX8MN_ANATOP_VIDEO_PLL 13 +#define IMX8MN_ANATOP_DRAM_PLL 14 +#define IMX8MN_ANATOP_GPU_PLL 15 +#define IMX8MN_ANATOP_M7_ALT_PLL 16 +#define IMX8MN_ANATOP_ARM_PLL 17 +#define IMX8MN_ANATOP_SYS_PLL1 18 +#define IMX8MN_ANATOP_SYS_PLL2 19 +#define IMX8MN_ANATOP_SYS_PLL3 20 +#define IMX8MN_ANATOP_AUDIO_PLL1_BYPASS 21 +#define IMX8MN_ANATOP_AUDIO_PLL2_BYPASS 22 +#define IMX8MN_ANATOP_VIDEO_PLL_BYPASS 23 +#define IMX8MN_ANATOP_DRAM_PLL_BYPASS 24 +#define IMX8MN_ANATOP_GPU_PLL_BYPASS 25 +#define IMX8MN_ANATOP_M7_ALT_PLL_BYPASS 26 +#define IMX8MN_ANATOP_ARM_PLL_BYPASS 27 +#define IMX8MN_ANATOP_SYS_PLL3_BYPASS 28 +#define IMX8MN_ANATOP_AUDIO_PLL1_OUT 29 +#define IMX8MN_ANATOP_AUDIO_PLL2_OUT 30 +#define IMX8MN_ANATOP_VIDEO_PLL_OUT 31 +#define IMX8MN_ANATOP_DRAM_PLL_OUT 32 +#define IMX8MN_ANATOP_GPU_PLL_OUT 33 +#define IMX8MN_ANATOP_M7_ALT_PLL_OUT 34 +#define IMX8MN_ANATOP_ARM_PLL_OUT 35 +#define IMX8MN_ANATOP_SYS_PLL3_OUT 36 +#define IMX8MN_ANATOP_SYS_PLL1_OUT 37 +#define IMX8MN_ANATOP_SYS_PLL1_40M 38 +#define IMX8MN_ANATOP_SYS_PLL1_80M 39 +#define IMX8MN_ANATOP_SYS_PLL1_100M 40 +#define IMX8MN_ANATOP_SYS_PLL1_133M 41 +#define IMX8MN_ANATOP_SYS_PLL1_160M 42 +#define IMX8MN_ANATOP_SYS_PLL1_200M 43 +#define IMX8MN_ANATOP_SYS_PLL1_266M 44 +#define IMX8MN_ANATOP_SYS_PLL1_400M 45 +#define IMX8MN_ANATOP_SYS_PLL1_800M 46 +#define IMX8MN_ANATOP_SYS_PLL2_OUT 47 +#define IMX8MN_ANATOP_SYS_PLL2_50M 48 +#define IMX8MN_ANATOP_SYS_PLL2_100M 49 +#define IMX8MN_ANATOP_SYS_PLL2_125M 50 +#define IMX8MN_ANATOP_SYS_PLL2_166M 51 +#define IMX8MN_ANATOP_SYS_PLL2_200M 52 +#define IMX8MN_ANATOP_SYS_PLL2_250M 53 +#define IMX8MN_ANATOP_SYS_PLL2_333M 54 +#define IMX8MN_ANATOP_SYS_PLL2_500M 55 +#define IMX8MN_ANATOP_SYS_PLL2_1000M 56 +#define IMX8MN_ANATOP_CLK_CLKOUT1_SEL 57 +#define IMX8MN_ANATOP_CLK_CLKOUT1_DIV 58 +#define IMX8MN_ANATOP_CLK_CLKOUT1 59 +#define IMX8MN_ANATOP_CLK_CLKOUT2_SEL 60 +#define IMX8MN_ANATOP_CLK_CLKOUT2_DIV 61 +#define IMX8MN_ANATOP_CLK_CLKOUT2 62 + #endif diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 3235d7de3b62..8c076225fd9e 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -402,4 +402,72 @@ #define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_ANATOP_CLK_DUMMY 0 +#define IMX8MP_ANATOP_CLK_24M 1 +#define IMX8MP_ANATOP_CLK_32K 2 +#define IMX8MP_ANATOP_AUDIO_PLL1_REF_SEL 3 +#define IMX8MP_ANATOP_AUDIO_PLL2_REF_SEL 4 +#define IMX8MP_ANATOP_VIDEO_PLL_REF_SEL 5 +#define IMX8MP_ANATOP_DRAM_PLL_REF_SEL 6 +#define IMX8MP_ANATOP_GPU_PLL_REF_SEL 7 +#define IMX8MP_ANATOP_VPU_PLL_REF_SEL 8 +#define IMX8MP_ANATOP_ARM_PLL_REF_SEL 9 +#define IMX8MP_ANATOP_SYS_PLL1_REF_SEL 10 +#define IMX8MP_ANATOP_SYS_PLL2_REF_SEL 11 +#define IMX8MP_ANATOP_SYS_PLL3_REF_SEL 12 +#define IMX8MP_ANATOP_AUDIO_PLL1 13 +#define IMX8MP_ANATOP_AUDIO_PLL2 14 +#define IMX8MP_ANATOP_VIDEO_PLL 15 +#define IMX8MP_ANATOP_DRAM_PLL 16 +#define IMX8MP_ANATOP_GPU_PLL 17 +#define IMX8MP_ANATOP_VPU_PLL 18 +#define IMX8MP_ANATOP_ARM_PLL 19 +#define IMX8MP_ANATOP_SYS_PLL1 20 +#define IMX8MP_ANATOP_SYS_PLL2 21 +#define IMX8MP_ANATOP_SYS_PLL3 22 +#define IMX8MP_ANATOP_AUDIO_PLL1_BYPASS 23 +#define IMX8MP_ANATOP_AUDIO_PLL2_BYPASS 24 +#define IMX8MP_ANATOP_VIDEO_PLL_BYPASS 25 +#define IMX8MP_ANATOP_DRAM_PLL_BYPASS 26 +#define IMX8MP_ANATOP_GPU_PLL_BYPASS 27 +#define IMX8MP_ANATOP_VPU_PLL_BYPASS 28 +#define IMX8MP_ANATOP_ARM_PLL_BYPASS 29 +#define IMX8MP_ANATOP_SYS_PLL1_BYPASS 30 +#define IMX8MP_ANATOP_SYS_PLL2_BYPASS 31 +#define IMX8MP_ANATOP_SYS_PLL3_BYPASS 32 +#define IMX8MP_ANATOP_AUDIO_PLL1_OUT 33 +#define IMX8MP_ANATOP_AUDIO_PLL2_OUT 34 +#define IMX8MP_ANATOP_VIDEO_PLL_OUT 35 +#define IMX8MP_ANATOP_DRAM_PLL_OUT 36 +#define IMX8MP_ANATOP_GPU_PLL_OUT 37 +#define IMX8MP_ANATOP_VPU_PLL_OUT 38 +#define IMX8MP_ANATOP_ARM_PLL_OUT 39 +#define IMX8MP_ANATOP_SYS_PLL3_OUT 40 +#define IMX8MP_ANATOP_SYS_PLL1_OUT 41 +#define IMX8MP_ANATOP_SYS_PLL1_40M 42 +#define IMX8MP_ANATOP_SYS_PLL1_80M 43 +#define IMX8MP_ANATOP_SYS_PLL1_100M 44 +#define IMX8MP_ANATOP_SYS_PLL1_133M 45 +#define IMX8MP_ANATOP_SYS_PLL1_160M 46 +#define IMX8MP_ANATOP_SYS_PLL1_200M 47 +#define IMX8MP_ANATOP_SYS_PLL1_266M 48 +#define IMX8MP_ANATOP_SYS_PLL1_400M 49 +#define IMX8MP_ANATOP_SYS_PLL1_800M 50 +#define IMX8MP_ANATOP_SYS_PLL2_OUT 51 +#define IMX8MP_ANATOP_SYS_PLL2_50M 52 +#define IMX8MP_ANATOP_SYS_PLL2_100M 53 +#define IMX8MP_ANATOP_SYS_PLL2_125M 54 +#define IMX8MP_ANATOP_SYS_PLL2_166M 55 +#define IMX8MP_ANATOP_SYS_PLL2_200M 56 +#define IMX8MP_ANATOP_SYS_PLL2_250M 57 +#define IMX8MP_ANATOP_SYS_PLL2_333M 58 +#define IMX8MP_ANATOP_SYS_PLL2_500M 59 +#define IMX8MP_ANATOP_SYS_PLL2_1000M 60 +#define IMX8MP_ANATOP_CLK_CLKOUT1_SEL 61 +#define IMX8MP_ANATOP_CLK_CLKOUT1_DIV 62 +#define IMX8MP_ANATOP_CLK_CLKOUT1 63 +#define IMX8MP_ANATOP_CLK_CLKOUT2_SEL 64 +#define IMX8MP_ANATOP_CLK_CLKOUT2_DIV 65 +#define IMX8MP_ANATOP_CLK_CLKOUT2 66 + #endif