[10/11] arm64: dts: imx8mn-bsh-smm-s2-common: Disable PMIC SNVS reset target state
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Message ID 20250512135005.1419006-11-michael@amarulasolutions.com
State New
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Series
  • Update imx8mn-bsh-smm boards
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Commit Message

Michael Nazzareno Trimarchi May 12, 2025, 1:50 p.m. UTC 
From: Wolfgang Birkner <wolfgang.birkner@bshg.com>

VDD_DRAM was disabled on standby, therefore the reference hardware did not wake
up reliable. Use PMIC reset target state READY instead of SNVS, to keep VDD_DRAM
active during standby.

Signed-off-by: Wolfgang Birkner <wolfgang.birkner@bshg.com>
---
 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 -
 1 file changed, 1 deletion(-)

Patch
diff mbox series 

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
index 65a612ca82747..0dc689f2cf628 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi
@@ -94,7 +94,6 @@  bd71847: pmic@4b {
 		pinctrl-0 = <&pinctrl_pmic>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
-		rohm,reset-snvs-powered;
 
 		#clock-cells = <0>;
 		clocks = <&osc_32k>;