From patchwork Tue May 20 15:06:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 4047 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 8E44F3F12A for ; Tue, 20 May 2025 17:07:18 +0200 (CEST) Received: by mail-wm1-f71.google.com with SMTP id 5b1f17b1804b1-441c122fa56sf28203695e9.2 for ; Tue, 20 May 2025 08:07:18 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1747753638; cv=pass; d=google.com; s=arc-20240605; b=LadinI1y/KA/iS0M+VB+vciwU9SACx6aFawftUvAsfaOym2PnpnO4wstvrN5pMcLYX Dl81UK7uIZGB6lMb4AZ+9xpgqAzGK7gHBvCPjYBauVxXzhKo7glMI5KyeNOGWIBDHB2g fR8eDx8wrswB/6FUKAHLap78r6VWjji95MNDZGwVYdU3Oqa8vdlWsTYMsmYdgHqfnTWJ f3yufXB8CMPcb0a7wWSUm6iWNP7lMxq7nSvLcN9989ZJYcdKo8cvuWt+5MFJLYhJjUBl rQPLUXnpF4U2jNCmRQ6jb8nyA7NooFumCKeHp0SKWuPXqgqtxjfik5T7XRLAxwdWoT8N vTOQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:message-id:date:subject:cc:to :from:dkim-signature; bh=Y7Gbz4jjj56X+7KYK5VtCgxGJ76d9sIiubnFc6v6WH8=; fh=s3mHlyP5NyXV/74kf66DlluVFI9bli+5HNG9GGjFe04=; b=P3gP0TR1S5WJPhFQuMTxskovaIK17i43B375T/b4NSAOc6kEdWSENzfXO7NXZWx5N4 H+0NVx2ZvFNLgeleAVl5RJ623tmD6bj88XgWyIWteuZ6FyY7QcKL7BRXWUDzFKYWKbS0 VYuU48HdfoUYMLs4Hqg9C9HZlWoVFAsEx3bxDJ4PZ3Kfedm9J6Jyyxnv6qzE3CGYRSjA 2kRqRA20kfEvimIxbPLf+3mXWeFMS9pcz8m7K/d3varKoobI6ewwKFG91veIduvssJou yBQ3vcV9JtvUZUFFTqLw8o15vHreFqZ7dW1HrsiEaaWxsNTR42DbId7qHBeGzM6LmnD1 VIng==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lAOlms4n; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1747753638; x=1748358438; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:message-id:date:subject:cc:to:from :from:to:cc:subject:date:message-id:reply-to; bh=Y7Gbz4jjj56X+7KYK5VtCgxGJ76d9sIiubnFc6v6WH8=; b=JxJsiJ4bMfDDWy5rldI5iBxP2dT0LEu31VGckXHneXP63s3cRP7FcXjaqBBJCNHPAK GBZ3bQbsCCYF+OlPLptFyL89qZG6TbELeYmSQ5w1g4ta8aXtecpEP5CcDM9+TQT1nlTp u5pHCd/sjC1pm4edFi8Z8B6rCUp4d23x+Z3nc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1747753638; x=1748358438; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :message-id:date:subject:cc:to:from:x-beenthere:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=Y7Gbz4jjj56X+7KYK5VtCgxGJ76d9sIiubnFc6v6WH8=; b=slfubJyTiqP6Jkr883HuuW1njrjndMqrkmZV8wygLTNa1hHwGrVA5dMt/7n/u4DTwL 1SHIJycQtX+jfCjfquFpLOm+SfTgaOCTN8Clpu28NIqVCniFkSOu88/q1HzQ5thZTEfl nywk1LSHwD/VHT+45Yas3m8A0IHVHDd12EMTvwW/WlLbvgvu9AKwKXZw6hIumBrPvSIm 8cuCOC1+aVGdYriiSY8vpfCiikq0yBOB6XJGlAvNp+DJNNqkljecdMsqn8rB2io7TwP/ XlqHs66z8d5EqMjI9fCAmsCsmIqUMF06IqzKSiT2liMZFT21ds+WHmiwnHeN9zMX7Wuw lAmg== X-Forwarded-Encrypted: i=2; AJvYcCWnrzgroa9+aihrOXyC5o6Qz3AGXvqya8FQqpLM0fRkRdZrlXkq9UXGidWOW0s1828xVzTO+HWG5yLmuXOE@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YzWUF0R6+F4G+ujExfDosdu5iTfi1e+eoVgPekTQPfAHLyx47aV tiXjdysOpK4/ObcYOU1b3b80Qyca5BxCB3hLRO2jH5/NNgDFl8ga9JaJMxWH74nLn+mw7w== X-Google-Smtp-Source: AGHT+IHpNllhKLzA8uZbMuuOPILgOkhBi2XYi7K0VaAYcZv/rTbV4De8ENmWaxUAYWQg4Dy5RsxU8A== X-Received: by 2002:a05:600c:5006:b0:442:f956:53f9 with SMTP id 5b1f17b1804b1-442fd64e4d3mr148491625e9.18.1747753637835; Tue, 20 May 2025 08:07:17 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h=AVT/gBFrDX80oBceV84QQURysfZQxfssR6LVcxK7CkVAEs1Itw== Received: by 2002:a05:600c:384b:b0:43c:f7b4:5d58 with SMTP id 5b1f17b1804b1-442f877a8e2ls31759395e9.1.-pod-prod-03-eu; Tue, 20 May 2025 08:07:16 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVA7d7g7r3QK0ChGvK0xTX7/3NICgswSB8aUsNMh53fjP7kMLaYP4bCXtYQolR2wiwDYf+GR91VJ1KNdDFd@amarulasolutions.com X-Received: by 2002:a05:600c:3e88:b0:43d:94:2d1e with SMTP id 5b1f17b1804b1-442fd627303mr163424225e9.13.1747753635206; Tue, 20 May 2025 08:07:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1747753635; cv=none; d=google.com; s=arc-20240605; b=djQJgyjtH6ql423OfBxkZ1OHXi/90XKBAn1bgqb3PH0uvahLFPOAxeKWK0Pwov2Slx qJETMxlahLrv0bYcjsJitOy1ZRtjQXTLUn6LSUEmAWEMsVlbfwAGTtWbjTvECq+m/auB 9cpDIqmGR2WCUT1kEifGC7G8W0WqLvrH+IUI51isB3mh6pXS2OW+/N52E2yY6yubeqk1 B9WLPjqriSsCeleOXPxXdtwX+xK5WhhfHz+VpNVPXC2bKhFxzkXSP1Ov/8XuwR1Cr5ko P4ING2xaUFs6ICR/tIV9CyU3ux1CbWv4v1p2cpxsI4GLuOKlR4DazznaxyBlZkVJrHl9 NwRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=umDfddv0eFDxPx8NQVdX6EweKq1K+Vo3liwjYi2BWEk=; fh=fQ99wXn4tRGbjl1gTQwZqg9FXftFD9A/wiN7Msk7hC8=; b=LdVqB0Qmk1UVSAf/MXJgHuUhk66YaDRMjK23ECWT1yJRM/Jta6KBCisIG/ZSa+CkpR Gg/3t7vZgpDZKv9TRm5kkINO96ZSM8lsiUdS0Lx4ehu2qHOyUbCECbqdN0J4rFHh2Lva H/pMX+gS/XTtEfLC3ZWtZpZ9rmgSNaTntjbq5OA+Sf5T9onE2vVlxNnsu7C9Lwl6F8sF TGVWAgV/F7UH2B6fXaegp2Wl2YB/W3QTnljvk0qv6QaCSAR1N1iU6JplSigeVrR2hfRp SnOyTAFy7yZIW0Wk3OxTBeri5d1cpfxKpvNBALA0Pw6872RnQsYhhoZBucmfTGQMdAxT ekgQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lAOlms4n; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-442fd4d53c4sor36585395e9.0.2025.05.20.08.07.15 for (Google Transport Security); Tue, 20 May 2025 08:07:15 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AJvYcCXAs9mwZXrwfupCbWVVGL8B5lHy9fPr3Cpi2tl4GPo5w1N0AdeVWXRrSQQfseH6FwsH1AUzRinClNQZiWQD@amarulasolutions.com X-Gm-Gg: ASbGncsd2dzBQ4hmXUBeWGKoo3uxiGF6aeGpHk8VMnuSHB+qQfNvJny3wGESWkjl81j Qt4l8hwVoCSl9IMsrJwYj6iD+cFKP87OlCiOunEyjEaZNbgQgRpNnpMf8WImQ+oufQ0zwt20VDf OQPB8xc5Y9ZbBc3XOyjl7372KyDjKtuaFEfKPN/rHOqmzpXQUM9FZL1J7TMxTK3LptuV6PLExnS Lf8BsWGyrnvTtKLzLH2/yIULeTOQhTyEmCJkRdRea0AJ8RDdkMN0U+a4HcY9+JtnX55EGjK8rkN C/NmHrdS+UbtK4xaasMEuGW1BaS/XaGprprK0JggqpX1PqCv6qGxRuBdI8c3gZRQvz/vbePrRdI ehSoVIXS/NOO0IxNFdKrHe7in1symzXvTYLKLae48 X-Received: by 2002:a05:600c:3c94:b0:43d:24d:bbe2 with SMTP id 5b1f17b1804b1-442fd6758d2mr130039405e9.28.1747753632967; Tue, 20 May 2025 08:07:12 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.amarulasolutions.com ([2.196.40.47]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a35e49262fsm16179766f8f.44.2025.05.20.08.07.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 May 2025 08:07:12 -0700 (PDT) From: Dario Binacchi To: u-boot@lists.denx.de Cc: Michael Bode , linux-amarula@amarulasolutions.com, Simon Holesch , michael@amarulasolutions.com, Dario Binacchi , Fabio Estevam , "NXP i.MX U-Boot Team" , Simon Glass , Stefano Babic , Tom Rini , Wolfgang Birkner Subject: [PATCH v2 1/4] board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD table Date: Tue, 20 May 2025 17:06:59 +0200 Message-ID: <20250520150709.988904-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=lAOlms4n; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Michael Trimarchi When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- Changes in v2: - Add 'static struct' globally in the module where the definitions can mabe static. - Use standard C comment style arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 + arch/arm/mach-imx/mx6/ddr.c | 3 + board/bsh/imx6ulz_smm_m2/spl.c | 260 ++++++++++++++++++------ 3 files changed, 203 insertions(+), 62 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index ad9c1ac906a3..bd3ff65bcd96 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -457,6 +457,8 @@ struct mx6_mmdc_calibration { u32 p1_mpwrdlctl; /* lpddr2 zq hw calibration */ u32 mpzqlp2ctl; + /* MDC Duty Cycle Control Register */ + u32 mpdccr; }; /* configure iomux (pinctl/padctl) */ diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 5a1258e002d2..749ceee0cdbf 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -1444,6 +1444,9 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1; mmdc0->mprddlctl = calib->p0_mprddlctl; mmdc0->mpwrdlctl = calib->p0_mpwrdlctl; + if (calib->mpdccr) + mmdc0->mpdccr = calib->mpdccr; + if (sysinfo->dsize > 1) { MMDC1(mpwldectrl0, calib->p1_mpwldectrl0); MMDC1(mpwldectrl1, calib->p1_mpwldectrl1); diff --git a/board/bsh/imx6ulz_smm_m2/spl.c b/board/bsh/imx6ulz_smm_m2/spl.c index 724841b57456..936e54662e98 100644 --- a/board/bsh/imx6ulz_smm_m2/spl.c +++ b/board/bsh/imx6ulz_smm_m2/spl.c @@ -31,70 +31,209 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); } -static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { - .grp_addds = 0x00000028, - .grp_ddrmode_ctl = 0x00020000, - .grp_b0ds = 0x00000028, - .grp_ctlds = 0x00000028, - .grp_b1ds = 0x00000028, - .grp_ddrpke = 0x00000000, - .grp_ddrmode = 0x00020000, - .grp_ddr_type = 0x000c0000, +struct dram_cfg_param { + unsigned int reg; + unsigned int val; }; -static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_dqm0 = 0x00000028, - .dram_dqm1 = 0x00000028, - .dram_ras = 0x00000028, - .dram_cas = 0x00000028, - .dram_odt0 = 0x00000028, - .dram_odt1 = 0x00000028, - .dram_sdba2 = 0x00000000, - .dram_sdclk_0 = 0x00000028, - .dram_sdqs0 = 0x00000028, - .dram_sdqs1 = 0x00000028, - .dram_reset = 0x000c0028, +struct dram_timing_info { + const struct dram_cfg_param *ddrc_cfg; + unsigned int ddrc_cfg_num; }; -static struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x00000000, - .p0_mpwldectrl1 = 0x00100010, - .p0_mpdgctrl0 = 0x414c014c, - .p0_mpdgctrl1 = 0x00000000, - .p0_mprddlctl = 0x40403a42, - .p0_mpwrdlctl = 0x4040342e, -}; +static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = { + /* IOMUX */ + + /* DDR IO Type: */ + {0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */ + {0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */ + + /* Clock: */ + {0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */ + + /* Address: */ + {0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */ + {0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */ + {0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */ + + /* Control: */ + {0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */ + + {0x020e0270, 0x00000000}, /* + * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured + * using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS + */ + + {0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */ + {0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */ + {0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */ + + /* Data Strobes: */ + {0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */ + {0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */ + {0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */ + + /* Data: */ + {0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */ + {0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */ + {0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */ + + {0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */ + {0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */ + + /* + * ============================================================================= + * DDR Controller Registers + * ============================================================================= + * Manufacturer:ISSI + * Device Part Number:IS43TR16640BL-125JBLI + * Clock Freq.: 400MHz + * Density per CS in Gb: 1 + * Chip Selects used:1 + * Number of Banks:8 + * Row address: 13 + * Column address: 10 + * Data bus width16 + * ============================================================================= + */ + + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request bit during + * MMDC set up + */ + + /* + * ============================================================================= + * Calibration setup + * ============================================================================= + */ + + {0x021b0800, 0xA1390003}, /* + * DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic + * HW ZQ calibration. + */ + + /* + * For target board, may need to run write leveling calibration to fine tune these + * settings. + */ + {0x021b080c, 0x00000000}, + + /* Read DQS Gating calibration */ + {0x021b083c, 0x41480148}, /* MPDGCTRL0 PHY0 */ + + /* Read calibration */ + {0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */ + + /* Write calibration */ + {0x021b0850, 0x4040362E}, /* MPWRDLCTL PHY0 */ + + /* + * Read data bit delay: 3 is the recommended default value, although out of reset + * value is 0 + */ + {0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */ + {0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */ + + /* Write data bit delay: */ + {0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */ + {0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */ + + /* DQS&CLK Duty Cycle */ + {0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */ + + /* Complete calibration by forced measurement: */ + {0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */ -static struct mx6_ddr_sysinfo ddr_sysinfo = { - .dsize = 0, - .cs1_mirror = 0, - .cs_density = 32, - .ncs = 1, - .bi_on = 1, - .rtt_nom = 1, - .rtt_wr = 0, - .ralat = 5, - .walat = 1, - .mif3_mode = 3, - .rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */ - .sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */ - .refsel = 1, - .refr = 3, + /* + * ============================================================================= + * Calibration setup end + * ============================================================================= + */ + + /* MMDC init: */ + {0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */ + {0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */ + {0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */ + {0x021b0010, 0xB66D0B63}, /* MMDC0_MDCFG1 */ + {0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */ + + /* + * MDMISC: RALAT kept to the high level of 5. + * MDMISC: consider reducing RALAT if your 528MHz board design allow that. + * Lower RALAT benefits: + * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 + * b. Small performance improvement + */ + {0x021b0018, 0x00211740}, /* MMDC0_MDMISC */ + {0x021b001c, 0x00008000}, /* + * MMDC0_MDSCR, set the Configuration request + * bit during MMDC set up + */ + {0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */ + {0x021b0030, 0x002F1023}, /* MMDC0_MDOR */ + {0x021b0040, 0x00000043}, /* Chan0 CS0_END */ + {0x021b0000, 0x82180000}, /* MMDC0_MDCTL */ + + {0x021b0890, 0x00400000}, /* MPPDCMPR2 */ + + /* Mode register writes */ + {0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */ + {0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */ + {0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */ + {0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */ + {0x021b001c, 0x04008040}, /* + * MMDC0_MDSCR, ZQ calibration command sent to + * device on CS0 + */ + {0x021b0020, 0x00007800}, /* MMDC0_MDREF */ + + {0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */ + + {0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */ + + {0x021b0404, 0x00011006}, /* + * MMDC0_MAPSR ADOPT power down enabled, + * MMDC will enter automatically to self-refresh + * while the number of idle cycle reached. + */ + + {0x021b001c, 0x00000000}, /* + * MMDC0_MDSCR, clear this register + * (especially the configuration bit as initialization + * is complete) + */ }; -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1333, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 13, - .coladdr = 10, - .pagesz = 2, - .trcd = 1350, - .trcmin = 4950, - .trasmin = 3600, +static struct dram_timing_info dram_timing_128mb = { + .ddrc_cfg = ddr_ddrc_cfg_128mb, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb), }; +static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info) +{ + int i; + const struct dram_cfg_param *ddrc_cfg = dram_timing_info->ddrc_cfg; + const int ddrc_cfg_num = dram_timing_info->ddrc_cfg_num; + + for (i = 0; i < ddrc_cfg_num; i++) { + debug("Writing 0x%x to register 0x%x\n", ddrc_cfg->val, + ddrc_cfg->reg); + writel(ddrc_cfg->val, ddrc_cfg->reg); + ddrc_cfg++; + } +} + +static void spl_dram_init(void) +{ + struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; + + clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */ + clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */ + + ddr_cfg_write(&dram_timing_128mb); +} + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -108,20 +247,17 @@ static void ccgr_init(void) writel(0xFFFFFFFF, &ccm->CCGR6); } -static void imx6ul_spl_dram_cfg(void) -{ - mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); -} - void board_init_f(ulong dummy) { ccgr_init(); + + /* DDR initialization */ + spl_dram_init(); + arch_cpu_init(); timer_init(); setup_iomux_uart(); preloader_console_init(); - imx6ul_spl_dram_cfg(); } void reset_cpu(void)