From patchwork Wed Sep 17 08:05:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 4307 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 19DC83F14F for ; Wed, 17 Sep 2025 10:05:45 +0200 (CEST) Received: by mail-ed1-f72.google.com with SMTP id 4fb4d7f45d1cf-62f760c363esf671351a12.0 for ; Wed, 17 Sep 2025 01:05:45 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1758096345; cv=pass; d=google.com; s=arc-20240605; b=VA88ZR0HoWESvfqXgcF4ZWWAArs1U+y7gPFBjH9wkOfJrgwUTdOhzU2GxmoG9J5PU8 71tJT3eUW/vbJJQEbqHDxWYWNzYLCeN9QlsXKzKc5Y9sSJeKWoJotZVtgkYxQV9Pvdpt T4h+McmXWksAHpxjQiWzTaOTxdfIVAAcUnN+kuCXLUIOLkm3sja2fmEO/6VNcsjFYyyO KIxOMf8r4vIS9DmG9Z41bMyEDMBCZlZCImjkEN7XIA2h7TB1Xtu1ppIE7dyMyxBBNFUN vNtScNDu0MDtf9ATLDWT2oFGOiHoq/yTEt3LYyCQmjAS6hsWAlAFzJ+fInq9NbQlm7wA I8Cw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=qN+uwctul0mboouksWJmgzE4mbbYiYLV+2AkFXHilkY=; fh=tZGGOQim6KuJuSGg81kcLk2VbyZcnc5aBMsIgJizInE=; b=YLTCxY/YLvirkkYKdnvpKOPLZHeKbDPSD7FadZm5MceQ00tsS+qaBwt2mcYAsD/aoa uBEe/6x5gcRxTO7X4VJEfwxiWrGWdAZgZQvNZs4U118uCChVr0n2mbYnbHYWNpAnIHG1 JXCPYkjD15HGahyVK0PGWYqeOtxHvpg3WeOrFFM9VeZgW8lHJeOFhIxQ7HKa96P04BrH 4YqjxY/BmiHdP7HXQRCLyKLYnQ/BjC2mo1mlu4X+z+Ze921xhfN0zlyjj0ppfSxkBAAe tRv46dLmjmdpVdSlAg9GDErU4/yPcwzNVBPr6qxpirRU9+YT+abZX41Ti0A7x3N5rrfM a8Tw==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NEiYpycQ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1758096345; x=1758701145; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=qN+uwctul0mboouksWJmgzE4mbbYiYLV+2AkFXHilkY=; b=pZCODlO9/XUtiO0h2jrh1c8US1sA0y5z39mhcn7PpcW73j/K4iR4PySEXrBf3wPPs9 6xlvSNzaSXUyhopwiZYmzX95QHlcxerrL1U2Q92McVEBXkkkJ1Lz+3zNR/uC9esZY+lM Q2jO/lnh1uRWhHxxMoYfOXfnKfGJFmdhFUCoo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758096345; x=1758701145; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qN+uwctul0mboouksWJmgzE4mbbYiYLV+2AkFXHilkY=; b=St8r3Mt93TRnOF0ScL5xoZaEOpUTgBQ5RCda3bz/wY0n//M9dkmmcIwYxiZgIToXGR GqqzSrndHp8ok36pp40qlaKCsX3T+rHM0xH8i2tWr+3Ktuk8cWnL9xJ1NAYei8nAgzJC Th7Gb9nhv+MG8s2nFYvdbAb3Kb8gVvz0KoKh3qKoOBHKMEkMpcAhxTV01tcecgHj0+7n vPrtYnynSYDwRYiccgl6Ri4ywR3UwdV7HUAxvSRRxVd1BUhLvcOx1Wy6MezV7VB8t7uV FUny2TenarrZBB7RGvCR79QXdUoAUVzlwTqHP4+YbaeOCFEJvNXbMFvlPyTxhaOBC7KA NoiA== X-Forwarded-Encrypted: i=2; AJvYcCVIuEGXg51B2JN41tJQHL761upWD8QmwAEqHwVIcC+wEd2cIxjiAV1jQd/RwVOOmkhj3aVqG1Iii+t4fy3V@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YwI+m/6FNo0DBq+Yr39/psNn+N71VwRkswGUQTVFDDMWMgOl1hR uywrHRLaSbygrVnvjn32J1sYSRNL9Zt1N53TfvjLNmRC0h8GmuufFFpteTG5jW83Xj+g9g== X-Google-Smtp-Source: AGHT+IFL/ETWOyozNwm9dYuFzAHpPSYHknoIc03uJ7D3WJ+eDw5q2hHiyggf0GTYCJOA3IUt2JwvjQ== X-Received: by 2002:a05:6402:2695:b0:61c:35c0:87c6 with SMTP id 4fb4d7f45d1cf-62f83e2ee22mr1569995a12.12.1758096343898; Wed, 17 Sep 2025 01:05:43 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h=ARHlJd7zU/lSTKh+Vp6o0qh0cWtXiAEVOXVICS82Po3hzhcYUA== Received: by 2002:a05:6402:30b4:b0:62f:30fd:30e5 with SMTP id 4fb4d7f45d1cf-62f30fd31e4ls2296568a12.2.-pod-prod-09-eu; Wed, 17 Sep 2025 01:05:41 -0700 (PDT) X-Received: by 2002:a17:907:7ba3:b0:b04:2b56:c43c with SMTP id a640c23a62f3a-b1bbda5a8edmr166659566b.56.1758096340917; Wed, 17 Sep 2025 01:05:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1758096340; cv=none; d=google.com; s=arc-20240605; b=YNP9vzDyYN+nScnEpWwZaPCdigpb9HDdIPRa4scsmz/F/DOdnTOyLc/XzNOG7fg/q/ K8fkwl0Gd1OWUMGwQ/Pq2C5o1mfvBAURWyaJBV+nWIUydk3OnCk6cEgkYm1MEg1koAfM oWrlCsePZmVK6dvDlURX/GHTV8WBaU7I4LcH9DlH1wnkTP994wURe6H9MByoSEigK1IP jBd4b9piHpzl8BAohfj5tdpRcdeLYsevGvYQIjpwsT28HTpqx99QcwtYf5cxx62vM+Lu 6ewIboPKyZjQ+7NQeDBYAQ/aG2sTFPj5rHAwkRJK9BIz2n42wjONmk6oeRzb0ckgj2EQ MoMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=kDNPkG1BJO1AhX7f67y0O0jm17yTyZBB5A5XJjEod98=; fh=07XXofEZG9d+QeVy8dz+2QB2lNQ+zt329x24x7giHEI=; b=iWpciLxbdoSZFIvYMN8AlqiBBEQ4FXBGmWUiHlcXIa9iyen7n1MCL1r+lSIVwgJ4JI pnm1n8IfOKxKjSOTuTM/CH5iuLXwxTjB5xeY8DE27aw+zSqfBaYCGDYf/eyj9Qqs6Bgy 9VkU0kTePBe00jXr0Kk+vSkZdigwLFHhP7dPEsKf3F1IbuR4c8nc539YWp6VgaWuQQeb NsaGEXc0XLOjd1cfdfA3TkoGh/4VqPsYBoaLbWvamAhLpsNHsImzVY3SenwPKwC5cJ/x AkD2x4dObtO2okD6MmRcJwVOsKoOo+alkMe27zYN1lFpG+gmCKoIYp5L3GH3fl2suArM VSFQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NEiYpycQ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-b07b32dcf3csor522261066b.9.2025.09.17.01.05.40 for (Google Transport Security); Wed, 17 Sep 2025 01:05:40 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGncuHeFU2xzPkUmgkloCPxtmZHYVlcd4q4jGLfAIpHrlzOP+rWFXQgpnh6C1kw4+ HFFGeneuOycytzxHFAt9gC//Betk3RLEQt0vCB2Ezk9CYMKDfae8Nrd6dgZKBycDsfULqpG0UbN mjhKSTXnmLnQWmdl7/C2T/3PoMzkHLEbvPh14vyGcb7nqSclo4ein5pQENFOrFvNOpY/ideXHnW gPKhu6MKxVZLD49BKxIwEywajG+Egff8YVkb4ftyJz6jkdj2Ep7Xa4rlv6RGPbWacQgxz2kwFB5 78Nkr7OlfOwmTrU1Szi9ngtf/rwELv+ENcvFzPxHRmXKVqqLfs9V4Gmt2ktQsrJ1TppkxJ80oG6 UB+KhwwXUruTg/9YQshgC+62cfaP3R1odORgBnxEC/fcDE+c+0MSufOA76Ag= X-Received: by 2002:a17:907:7b8c:b0:b04:6338:c95a with SMTP id a640c23a62f3a-b1bbc5490a6mr145293166b.45.1758096340361; Wed, 17 Sep 2025 01:05:40 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:6474:ebbf:1215:4a13:8ee5:da2a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07e1aed5ffsm924936766b.81.2025.09.17.01.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 01:05:40 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Frank Li , Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v4 2/6] Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros Date: Wed, 17 Sep 2025 10:05:07 +0200 Message-ID: <20250917080534.1772202-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> References: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=NEiYpycQ; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Replace opencoded masking and shifting, with BIT(), GENMASK(), FIELD_GET() and FIELD_PREP() macros. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- (no changes since v2) Changes in v2: - Add Reviewed-by tag of Frank Li. - Move the patch right after the one fixing the typo according to Frank Li's suggestions. drivers/input/touchscreen/imx6ul_tsc.c | 96 +++++++++++++++----------- 1 file changed, 54 insertions(+), 42 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchscreen/imx6ul_tsc.c index c2c6e50efc54..e2c59cc7c82c 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -20,25 +21,23 @@ #include /* ADC configuration registers field define */ -#define ADC_AIEN (0x1 << 7) +#define ADC_AIEN BIT(7) +#define ADC_ADCH_MASK GENMASK(4, 0) #define ADC_CONV_DISABLE 0x1F -#define ADC_AVGE (0x1 << 5) -#define ADC_CAL (0x1 << 7) -#define ADC_CALF 0x2 -#define ADC_12BIT_MODE (0x2 << 2) -#define ADC_CONV_MODE_MASK (0x3 << 2) +#define ADC_AVGE BIT(5) +#define ADC_CAL BIT(7) +#define ADC_CALF BIT(1) +#define ADC_CONV_MODE_MASK GENMASK(3, 2) +#define ADC_12BIT_MODE 0x2 #define ADC_IPG_CLK 0x00 -#define ADC_INPUT_CLK_MASK 0x3 -#define ADC_CLK_DIV_8 (0x03 << 5) -#define ADC_CLK_DIV_MASK (0x3 << 5) -#define ADC_SHORT_SAMPLE_MODE (0x0 << 4) -#define ADC_SAMPLE_MODE_MASK (0x1 << 4) -#define ADC_HARDWARE_TRIGGER (0x1 << 13) -#define ADC_AVGS_SHIFT 14 -#define ADC_AVGS_MASK (0x3 << 14) +#define ADC_INPUT_CLK_MASK GENMASK(1, 0) +#define ADC_CLK_DIV_8 0x03 +#define ADC_CLK_DIV_MASK GENMASK(6, 5) +#define ADC_SAMPLE_MODE BIT(4) +#define ADC_HARDWARE_TRIGGER BIT(13) +#define ADC_AVGS_MASK GENMASK(15, 14) #define SELECT_CHANNEL_4 0x04 #define SELECT_CHANNEL_1 0x01 -#define DISABLE_CONVERSION_INT (0x0 << 7) /* ADC registers */ #define REG_ADC_HC0 0x00 @@ -65,19 +64,26 @@ #define REG_TSC_DEBUG_MODE 0x70 #define REG_TSC_DEBUG_MODE2 0x80 +/* TSC_MEASURE_VALUE register field define */ +#define X_VALUE_MASK GENMASK(27, 16) +#define Y_VALUE_MASK GENMASK(11, 0) + /* TSC configuration registers field define */ -#define DETECT_4_WIRE_MODE (0x0 << 4) -#define AUTO_MEASURE 0x1 -#define MEASURE_SIGNAL 0x1 -#define DETECT_SIGNAL (0x1 << 4) -#define VALID_SIGNAL (0x1 << 8) -#define MEASURE_INT_EN 0x1 -#define MEASURE_SIG_EN 0x1 -#define VALID_SIG_EN (0x1 << 8) -#define DE_GLITCH_2 (0x2 << 29) -#define START_SENSE (0x1 << 12) -#define TSC_DISABLE (0x1 << 16) +#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8) +#define DETECT_5_WIRE_MODE BIT(4) +#define AUTO_MEASURE BIT(0) +#define MEASURE_SIGNAL BIT(0) +#define DETECT_SIGNAL BIT(4) +#define VALID_SIGNAL BIT(8) +#define MEASURE_INT_EN BIT(0) +#define MEASURE_SIG_EN BIT(0) +#define VALID_SIG_EN BIT(8) +#define DE_GLITCH_MASK GENMASK(30, 29) +#define DE_GLITCH_2 0x02 +#define START_SENSE BIT(12) +#define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 +#define STATE_MACHINE_MASK GENMASK(22, 20) struct imx6ul_tsc { struct device *dev; @@ -112,19 +118,20 @@ static int imx6ul_adc_init(struct imx6ul_tsc *tsc) adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG); adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK); - adc_cfg |= ADC_12BIT_MODE | ADC_IPG_CLK; - adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK); - adc_cfg |= ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE; + adc_cfg |= FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) | + FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK); + adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE); + adc_cfg |= FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8); if (tsc->average_enable) { adc_cfg &= ~ADC_AVGS_MASK; - adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT; + adc_cfg |= FIELD_PREP(ADC_AVGS_MASK, tsc->average_select); } adc_cfg &= ~ADC_HARDWARE_TRIGGER; writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); /* enable calibration interrupt */ adc_hc |= ADC_AIEN; - adc_hc |= ADC_CONV_DISABLE; + adc_hc |= FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE); writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); /* start ADC calibration */ @@ -164,19 +171,21 @@ static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc) { u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4; - adc_hc0 = DISABLE_CONVERSION_INT; + adc_hc0 = FIELD_PREP(ADC_AIEN, 0); writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); - adc_hc1 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_4; + adc_hc1 = FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4); writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); - adc_hc2 = DISABLE_CONVERSION_INT; + adc_hc2 = FIELD_PREP(ADC_AIEN, 0); writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); - adc_hc3 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_1; + adc_hc3 = FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1); writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); - adc_hc4 = DISABLE_CONVERSION_INT; + adc_hc4 = FIELD_PREP(ADC_AIEN, 0); writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); } @@ -188,13 +197,16 @@ static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc) static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) { u32 basic_setting = 0; + u32 debug_mode2; u32 start; - basic_setting |= tsc->measure_delay_time << 8; - basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE; + basic_setting |= FIELD_PREP(MEASURE_DELAY_TIME_MASK, + tsc->measure_delay_time); + basic_setting |= AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); - writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); + debug_mode2 = FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN); @@ -250,7 +262,7 @@ static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc) usleep_range(200, 400); debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2); - state_machine = (debug_mode2 >> 20) & 0x7; + state_machine = FIELD_GET(STATE_MACHINE_MASK, debug_mode2); } while (state_machine != DETECT_MODE); usleep_range(200, 400); @@ -278,8 +290,8 @@ static irqreturn_t tsc_irq_fn(int irq, void *dev_id) if (status & MEASURE_SIGNAL) { value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE); - x = (value >> 16) & 0x0fff; - y = value & 0x0fff; + x = FIELD_GET(X_VALUE_MASK, value); + y = FIELD_GET(Y_VALUE_MASK, value); /* * In detect mode, we can get the xnur gpio value,