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[209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-b07b32995eesor753832066b.11.2025.09.17.01.05.44 for (Google Transport Security); Wed, 17 Sep 2025 01:05:44 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: ASbGnctQ7Y0rlPwVs+zPNRyF5VHG2Ivz1rP5K30kNddwDndlG/K51GBY2u6arK9/le1 tWGFzSYcHjhHQQxDrTRHmSt1LutCjv3fst1Ye/nV6a55Xabc+lxUMvWQKqRcM1w8CpSZg03rpKt bQ/4f/aOxYDrtSuO98pdJkYAXbxznzN4cY0VxxLnKFj8JL43w9jkT7mchwCAt2Yq4hEMhoUrLgo QlWbrAxRVHb3cHYNfh08NpkzP6hXO1RuNWC/FciostKQq2f8T6Ae+Vv5XIUxfWrNJAolQU67i0g 2o95nRx5o1fBCgnfGEY5F18XfETIuUXzbZQO0+dfpMuym2WBtScfwfayvTTMhJlGYlGetYB/jaF 2zDihfXMKW1vYB8c1KL12Y/vvT+qR6lWNuMvCkPS1Yc5iv67lTopJfJuN34I= X-Received: by 2002:a17:906:d555:b0:afe:ef8a:ac69 with SMTP id a640c23a62f3a-b1bb7d419ddmr158716766b.43.1758096343566; Wed, 17 Sep 2025 01:05:43 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:6474:ebbf:1215:4a13:8ee5:da2a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07e1aed5ffsm924936766b.81.2025.09.17.01.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 01:05:43 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Frank Li , Dario Binacchi , Conor Dooley , Dmitry Torokhov , Fabio Estevam , Haibo Chen , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v4 4/6] dt-bindings: touchscreen: fsl,imx6ul-tsc: support glitch thresold Date: Wed, 17 Sep 2025 10:05:09 +0200 Message-ID: <20250917080534.1772202-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> References: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Cx+nGiux; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=pass header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Support the touchscreen-glitch-threshold-ns property. Drivers must convert this value to IPG clock cycles and map it to one of the four discrete thresholds exposed by the TSC_DEBUG_MODE2 register: 0: 8191 IPG cycles 1: 4095 IPG cycles 2: 2047 IPG cycles 3: 1023 IPG cycles Signed-off-by: Dario Binacchi Reviewed-by: Conor Dooley --- Changes in v4: - Adjust property description following the suggestions of Conor Dooley and Frank Li. - Update the commit description. Changes in v3: - Remove the final part of the description that refers to implementation details. .../bindings/input/touchscreen/fsl,imx6ul-tsc.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml index 678756ad0f92..1975f741cf3d 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.yaml @@ -62,6 +62,20 @@ properties: description: Number of data samples which are averaged for each read. enum: [ 1, 4, 8, 16, 32 ] + touchscreen-glitch-threshold-ns: + description: | + Minimum duration in nanoseconds a signal must remain stable + to be considered valid. + + Drivers must convert this value to IPG clock cycles and map + it to one of the four discrete thresholds exposed by the + TSC_DEBUG_MODE2 register: + + 0: 8191 IPG cycles + 1: 4095 IPG cycles + 2: 2047 IPG cycles + 3: 1023 IPG cycles + required: - compatible - reg