From patchwork Sun Jan 11 07:33:38 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 4425 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id D56B840D1C for ; Sun, 11 Jan 2026 08:33:48 +0100 (CET) Received: by mail-ed1-f70.google.com with SMTP id 4fb4d7f45d1cf-650a191e47csf5038449a12.3 for ; Sat, 10 Jan 2026 23:33:48 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1768116828; cv=pass; d=google.com; s=arc-20240605; b=KxS9iuolt0LRQsLMKQOsf5IyxM4UbVHn4B6e8asc2SQ5GLYrrmpMC/8yufzyQ3lcjI G0BrqaPSkiGvDP2ARWItPKjN7R9MbCaT7WeB4quVntqFZGiBnPJSHXeL35BvnqzX2oBb hC/3bUsAr9TI+9BKrcQ+ylfsFGL6j8FCkMUQ+v2k7CsWwTZeGKy+m8cAUhNVdC6HxJzV MviZZow9MWf8WWm9wOOx+vzQ99iKKQX6q1ww1FFFQyY+WSefaP9N14TUkUA/5q+IWjYI ncowzn9qDMRWLPMBfdpeWPX8+fvPG/W8RpyFjbmYQTzLkR8rDuXedAeG4dRW731tzSlC pyJA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=jbjCCvzQ+dYQPqY2hpVriPQzd1IChyj6FVZIKtfmxcc=; fh=Tp1tBD1Ykv85xR7Ij4H7t9kS2FOzc0NrBVwIK3pxleE=; b=NKYSCbVPnWZbh2pQhKn2p/74IsPxMgqgM17VA+Gn4r4AKDglJxyF2ffgZYefFVx0Db ALHI4R8ytgjVIkVZdF7HIKBiDUwyAS++LrSKK57ctR3OhYNsXXosf9YQTk+r0wvSEwq9 lTjbNDOTun6lMIxWd7DTdu8EaCNTBx22FvO8OmEJpWVIFQbFj2DckXEksMURlclxTw6s Y0BcAVvgMraWxD3W+f0OatzfUIAQgqVsqFAK3VIhrvZ+zkGpa7UNQFnR9AsRdXRIhSgh nWEdxg6pj/tSH8e1wcFoM8W8XDOHf7i0lJCcUUGhvBWSmVLLddAckKOCqejwZurc55Ys 5VwA==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Hi4h6S7a; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1768116828; x=1768721628; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=jbjCCvzQ+dYQPqY2hpVriPQzd1IChyj6FVZIKtfmxcc=; b=quSiDrCyAv9XeAnDpfKTWoG8m2mteEAGFqtA27vLLpILdx6GTW1gGNNc//ZzSsuSen UHMtrTq3HkbmoghEsCjQPXuy00uQqY/AWit5VVsv1xlo9dB9hEaDkndQGPG51CN7yuSS gJkNBH2+YK+KWiGSZQ8XJ4RyyVYEistzeY8NE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768116828; x=1768721628; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jbjCCvzQ+dYQPqY2hpVriPQzd1IChyj6FVZIKtfmxcc=; b=FxRvElo6KG+MVpIcVzB930FqftYLQF11vii5Uy/INK5+opPphf+G+82TeT5AClCsTv cfmmIX/CXNnRVEvUTYIPTJekkW20qSMzQMdnRv7vqBpH6J6GGx0c7HGVfbHdYyN3GZW8 wMpMSDGzvb3cqg+XGWgkAdSqrqA6DT2///5p44kJLNViSHIejv5wBuvfqpRch/V97ogu T5JyMYaZ5PMeQLH4D2P8r2gPmNm4LQDHYB5WNMt/O7A6dC3beCa6JZJep/GS3UNLok72 gRde53+Su88fvSebQEffeZmoDuUy/icMfq+L/MvAt/1psjGZoGEkWeKQJVNuV9W9LU4m ZASA== X-Forwarded-Encrypted: i=2; AJvYcCXGsFUmsxdKLhGCQkOCfNMYRz0i7epoyz3KrXbf78HNjLQZdbpSVpedrSKNVZIkoHClNaeKcJjQkcmBJCvj@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YyC1dLb4RIQ8JK+Eivi0O5CAD5rHlalr9FYOOly0wzJun+qoISo ElS2+sOBXCPVaFH34bbjQZOQhYV+DXwpT3IcC5fxKSZyeCxBT7Iui+D1Mgr/gteZPth4/evQI5b lgQ== X-Google-Smtp-Source: AGHT+IF+5sDSVtBTq2FFQNu3PN+rxDUMkVIxOdXiC7aVvQgjsFyEYkhlL4nTIAkvUjRVfVTNrmqUJw== X-Received: by 2002:a05:6402:1454:b0:649:81d2:ce4e with SMTP id 4fb4d7f45d1cf-65097dc6524mr12602090a12.2.1768116828367; Sat, 10 Jan 2026 23:33:48 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com; h="AV1CL+EQsLmij3KnGD/+fPtjGm/KivLjM07Qk0oMhK4MA0AA+w==" Received: by 2002:a05:6402:553:b0:641:2745:845e with SMTP id 4fb4d7f45d1cf-65074317d1bls2819570a12.0.-pod-prod-03-eu; Sat, 10 Jan 2026 23:33:46 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX3oD52LSqGxSzUlMol1mpraCcZXabQS2zQ8V81GOi3kTKPezcvDpTCpXBTKs3iE7tVJ00evys/lj0lBbO4@amarulasolutions.com X-Received: by 2002:a05:6402:51c9:b0:64d:2889:cf50 with SMTP id 4fb4d7f45d1cf-65097e574f6mr11469223a12.23.1768116826120; Sat, 10 Jan 2026 23:33:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1768116826; cv=none; d=google.com; s=arc-20240605; b=MO8EepvIfZn8PHQWXBazmHM4FmbBaatEoMx2WuvNt1KP5LGvOR+ausm7/433Qp6Njm 1oE1J1BV1HISA+tpziGaWWvCdaQ+EFS4Pov7OfxsxGQCjD3fvKWhDGyrwa5cLqOYWTEn wAIPcJjA2Su7mUk9oFQVtBiEuAYiE0s5q1D/FDW6jS9C5g8y5DFdTUHUBt0uI3yQ5V2g RJQAvFMUH/fbbe5jxfor1LMyYY9CC6DiLW8E/eRnpRH5ukUXA/yFJo/RF7PZodGF4DmY OtgCZBsv7YTR4sLtojwi/FPXydMLpqCC7X2lV0wdIFAbOwsfzT9y2d2BqUGvvq7Wd4uv 7Hcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4OpZl3MJRE5IEA/t9sJyTFgGpgwLTq3A633zlNV1dLY=; fh=Q4e4BQZrRSVDtrNtVWvlVLoevVp/0GUzkTNX+8b3Z7U=; b=TlSWLh4tbqoZ/4zDmIgs2mTqhk5eN083rlECxfurZqXAMC8JeJ/s46GLDUJk4nH2pA 2XZnKdHaLW167R3bS7O+AWGRBVwa5tbA+SWSMi9nj0AftsxI2sI95/YssO/iRIAt1A0Y Lwk3yHs2rMiELhMPbaQyzarS+7A1TfiDwv96VyNupdTOUcy0T5Vei3his/4rPakepDjZ xuph1ti8k+znOsJWrPxPILr2O1p4enFFMGdw5mt9XYkYmTX5z0+oEBN3NB+Pb9m8kxcg 95tUJf85l0kow2/G5IR/JZ+kUaKT2FVoCfQ3NQrNRswG1NrUG2W+3Aiw8CalZvkMLuNd YNSQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Hi4h6S7a; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id 4fb4d7f45d1cf-6507b226e89sor4724973a12.0.2026.01.10.23.33.46 for (Google Transport Security); Sat, 10 Jan 2026 23:33:46 -0800 (PST) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AJvYcCVSvXGEsAxDV97vOjVrFQvt0C4aphDipckLGdsqg+KlaeRlvd2QmGPmf3UUJS94p1IBqTPnHTELCjjaJczN@amarulasolutions.com X-Gm-Gg: AY/fxX77odEQPAJ1Z5f5kENQUQKGzIVfFYsGeeQiKCGfsh+Nk/F7iLWS9LcJiRHUYMp kyjCVF7dqu1kP2VUAqi7VPH9Fhn9iuO5QkHXB5Y9qtqHDiZ2xqK1l4ET28z+ES1Hrie0EKH8nvL 24CyMGpvXrXJU+A2T1AtsQJdfuO+sh65o+JdpMlJoU068j8yvxc9KJryyYJdC7kClZ1jOpnXLHf mqWn4uXGvIHwFcU4wgW6REJObKTjyoqxUuIuH7K87tuuUWG1fcJdZ1G9MmPuBojxkNA7f/eKVIC vSxEd8igejFd81GhYVeW6VWzMeSNO6bMNOD0nShE7+K7pDqMaIUAi7654/bdb16nbPF3Cx+p6wp 3Zp/5YWzNTP3u985qwsGhw3lPJJ4IWl7NtPGSqi+C5Dfu3H0eCji8uL28Q03l5A52KGY6H5vjQs K0N6YfI8YiktozKlhCsdda0vCY3pH1WuPBPkHLD4vYXlHhWYl8FpYp6f9+anBZN7YO50s6JMoqZ ElSkfSjzXwYzUhruB9NMQZBrjYLYqylTYdGlgQ+PhUifHAwyhxa6CsR2w== X-Received: by 2002:a05:6402:2345:b0:649:6ac4:79af with SMTP id 4fb4d7f45d1cf-65097dc62abmr13696924a12.6.1768116825668; Sat, 10 Jan 2026 23:33:45 -0800 (PST) Received: from panicking.homenet.telecomitalia.it (host-87-5-117-220.retail.telecomitalia.it. [87.5.117.220]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507bf6d683sm14548782a12.34.2026.01.10.23.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Jan 2026 23:33:44 -0800 (PST) From: Michael Trimarchi To: Peng Fan , Jaehoon Chung Cc: Tom Rini , Dario Binacchi , u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Michael Trimarchi Subject: [PATCH 1/2] power: regulator: pfuze100: support high voltage range bit Date: Sun, 11 Jan 2026 08:33:38 +0100 Message-ID: <20260111073339.1297089-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260111073339.1297089-1-michael@amarulasolutions.com> References: <20260111073339.1297089-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Hi4h6S7a; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The PFUZE100/200/3000 family of PMICs allow switching regulators (specifically SW2, SW3A/B, SW4 on PFUZE100/200 and SW2 on PFUZE3000) to operate in a "high" voltage range mode. This mode is indicated by a specific bit in the voltage selection register (bit 3 for PFUZE3000, bit 6 for others). When this bit is set: - PFUZE100/200 switches from a 25mV step to a 50mV step, with a different minimum voltage (800mV). - PFUZE3000 SW2 switches to a completely different non-linear voltage table. Currently, the driver uses static descriptors that assume the low/default range. This results in incorrect voltage readings and settings if the PMIC is configured for the high range. This patch updates the driver to: 1. Identify regulators with high-bit support via a new `hi_bit` flag. 2. Read the register during probe to detect the current range configuration. 3. Dynamically update the regulator descriptor (step, mask, min_uV, or table) to match the active range. This aligns the U-Boot driver behavior with the Linux kernel implementation. Signed-off-by: Michael Trimarchi --- drivers/power/regulator/pfuze100.c | 66 ++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 18 deletions(-) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index f864b1d8834..63d39c21bb8 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -18,6 +18,7 @@ * * @name: Identify name for the regulator. * @type: Indicates the regulator type. + * @hi_bit: Indicate if support hi voltage range. * @uV_step: Voltage increase for each selector. * @vsel_reg: Register for adjust regulator voltage for normal. * @vsel_mask: Mask bit for setting regulator voltage for normal. @@ -29,6 +30,7 @@ struct pfuze100_regulator_desc { char *name; enum regulator_type type; + bool hi_bit; unsigned int uV_step; unsigned int vsel_reg; unsigned int vsel_mask; @@ -54,10 +56,11 @@ struct pfuze100_regulator_plat { .voltage = (vol), \ } -#define PFUZE100_SW_REG(_name, base, step) \ +#define PFUZE100_SW_REG(_name, base, step, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .hi_bit = (hbit), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x3F, \ @@ -65,10 +68,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x3F, \ } -#define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \ +#define PFUZE100_SWB_REG(_name, base, mask, step, voltages, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .hi_bit = (hbit), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = (mask), \ @@ -155,15 +159,19 @@ static unsigned int pfuze3000_sw2lo[] = { 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000 }; +static unsigned int pfuze3000_sw2hi[] = { + 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000, +}; + /* PFUZE100 */ static struct pfuze100_regulator_desc pfuze100_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000), - PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000), - PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), + PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, true), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), @@ -176,11 +184,11 @@ static struct pfuze100_regulator_desc pfuze100_regulators[] = { /* PFUZE200 */ static struct pfuze100_regulator_desc pfuze200_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), @@ -195,9 +203,9 @@ static struct pfuze100_regulator_desc pfuze200_regulators[] = { static struct pfuze100_regulator_desc pfuze3000_regulators[] = { PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000), PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000), - PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo), + PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo, true), PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000), @@ -246,9 +254,10 @@ static int pfuze100_regulator_probe(struct udevice *dev) struct dm_regulator_uclass_plat *uc_pdata; struct pfuze100_regulator_plat *plat = dev_get_plat(dev); struct pfuze100_regulator_desc *desc; - int i, size; + int i, size, val, sw_hi = 0x40; + int version = dev_get_driver_data(dev_get_parent(dev)); - switch (dev_get_driver_data(dev_get_parent(dev))) { + switch (version) { case PFUZE100: desc = pfuze100_regulators; size = ARRAY_SIZE(pfuze100_regulators); @@ -260,6 +269,7 @@ static int pfuze100_regulator_probe(struct udevice *dev) case PFUZE3000: desc = pfuze3000_regulators; size = ARRAY_SIZE(pfuze3000_regulators); + sw_hi = 1 << 3; break; default: debug("Unsupported PFUZE\n"); @@ -281,6 +291,26 @@ static int pfuze100_regulator_probe(struct udevice *dev) uc_pdata = dev_get_uclass_plat(dev); uc_pdata->type = desc[i].type; + + /* SW2~SW4 high bit check and modify the voltage value table */ + if (desc[i].hi_bit) { + val = pmic_reg_read(dev->parent, desc[i].vsel_reg); + if (val < 0) { + printf("Fails to read from the register.\n"); + return -EIO; + } + + if (val & sw_hi) { + if (version == PFUZE3000) { + desc[i].volt_table = pfuze3000_sw2hi; + } else { + desc[i].uV_step = 50000; + desc[i].vsel_mask = 0x7; + uc_pdata->min_uV = 800000; + } + } + } + if (uc_pdata->type == REGULATOR_TYPE_BUCK) { if (!strcmp(dev->name, "swbst")) { uc_pdata->mode = pfuze_swbst_modes;