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[209.85.220.41]) by mx.google.com with SMTPS id 4fb4d7f45d1cf-683c8695467sor644965a12.3.2026.05.15.08.10.56 for (Google Transport Security); Fri, 15 May 2026 08:10:56 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Gm-Gg: Acq92OGmwp6YL3KtjyHMS7JzojNi4JNHW7INnNJsCwa37igc2W1sUNl2filDtxyOiNM 08xnma5VEiEkEnIZGjDpKQEUVDT7U0ECp4B3RA9lK8CjeeJWfyd9HGKDbX20L9CO9WrsD5aIOxm LhBTiFtBVJmyUwZYEr72ZTDshSSzHAnW7TY5SwZnj4W7zmlo2qwI+jwsA4jD/9QHE80PYWra0AU 00u4vKVo431Ha68rShFVsyVDg9NXp+TbfF4QjrPittVvs9oIVm0SL4+lsxEZVYRbW6vuqXvT0KS th5jrLEHqa7J12ip5ytD7/MX2jnRluqkml7v5fCifHNMmzHouwE8mRJG8q3j6F4rO6hWCe+r/Jq Nn2RWsHlWew3jwPsQ2IwTBXStr7xVx72GGxdf4rvdLov9r+4db+h1iiQfaPI9LPwk0LEjCn7k8j mxRF57N1H8EBfm5UMy872Kh7LgeC2X81xCWswQNDa2F2Aed2w+huX4G6afTrRjaoWB8WEu9Bfyg yi8xIceT65jqUuEu+1buWeXJ4YMnY+303k9+hHCTFCAR21E X-Received: by 2002:a05:6402:370a:b0:683:e55a:d165 with SMTP id 4fb4d7f45d1cf-683e55ad541mr1670583a12.2.1778857855660; Fri, 15 May 2026 08:10:55 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.112]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-68310b4069dsm2184189a12.1.2026.05.15.08.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 May 2026 08:10:54 -0700 (PDT) From: Dario Binacchi To: michael@amarulasolutions.com Cc: linux-amarula@amarulasolutions.com, roberto.bonacina@wh.com, Dario Binacchi Subject: [PATCH 05/15] arm64: dts: st: add ltdc pins for stm32mp25 Date: Fri, 15 May 2026 17:10:26 +0200 Message-ID: <20260515151036.1851820-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260515151036.1851820-1-dario.binacchi@amarulasolutions.com> References: <20260515151036.1851820-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Ncfrv4ms; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add the LTDC pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index db485b9ed904..2e334c2bffae 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -260,6 +260,77 @@ pins { }; }; + /omit-if-no-ref/ + ltdc_pins_a: ltdc-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins {