From patchwork Thu Sep 3 15:32:16 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 4837 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 315C93F0E6 for ; Thu, 3 Sep 2026 17:39:03 +0200 (CEST) Received: by mail-wm1-f71.google.com with SMTP id 5b1f17b1804b1-4994cf6cdb9sf17750475e9.3 for ; Thu, 03 Sep 2026 08:39:03 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1788449943; cv=pass; d=google.com; s=arc-20260327; b=McRrkD1ghIs+oBxGCpovyJDoy45A3UKoxicuZZGnYCW0gSpjDcfOtE4SeNzvnTF21M xxyf2tkyCUAq7O4hPSvqqRyLvsU/Ir+ZTUKOP4E0xRvK8RNqTdIlxEFf/hq2QK1WYThX hInLTFjMFXlhilZw/2ww8xnK7s7D296GXTydOVI7iqL/lt+MVhMui6M9+jkLa46vGxv0 JnC+pzUbsG0YvBEY+oxSaUTimc6dPoCnigAOHBlqMmD3FROT4saTny1EdkL7d8eYu4TT iizPrj/LEh19tKmUu725TczW3OU4+p3GFdP/TAVKzQh/1/1LEwqPdzajKXgIjy0+HGGS hGxg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20260327; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Y1d8X8uM9FkKm89DOGhCID8lQF7Afpw9NOOSEnYoGSs=; fh=0cBepB90VzB6ZzI0i0NcaB3TClEbr8MQJf2z2X6dR9M=; b=NY2i7/F7MmF/wy91jmyYm9bpfYHrhqi4+ud2tJZxF6ySdl98kT8YsZV45itaRY7Sbs HM9j4ABrT9O4IhA19JdhZ+8zD8l/ObVm6haDPzG1HNHSTcu4Dg4rDIaRRq++rVhuO1wG sRyXoBoWUCKRMf3lOGXhwEvB3fKvS3iwgjFuEyNp8/4T9TOlESqkORPrID02NqHUKBC+ Zg0Cts8DIWL82aPt5jjW1A34CgRdkw/QLmU3W7kmRamAVgCzqASShbAS3JZstypdMZlG AUvVKb7R2DRJQ9tKFwsqQLGyyBI73Q1ild0lMNbEYTf874LV/GisRNrgy2BM8WO/JRvT 02Mg==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=llI208DO; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1788449943; x=1789054743; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:content-type :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to:content-type; bh=Y1d8X8uM9FkKm89DOGhCID8lQF7Afpw9NOOSEnYoGSs=; b=SOAnsbqvIY20THJiKU6MQL4tKVc7F4+8kYs8OI6eKY1a8cCe7sx2tCTdmCfvkGnTNo zD8WqyI/mpXa9Qq3DZlw3avzH01rRlW72cMxWqqOmqf1Q4+aVnA/HQ9+p9/xd3JqvlzB 96ykeezI+vK329ftmsYVXh+NW9Tts/E2gQxd8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788449943; x=1789054743; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :content-type:x-original-authentication-results:x-original-sender :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-gg:x-beenthere:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Y1d8X8uM9FkKm89DOGhCID8lQF7Afpw9NOOSEnYoGSs=; b=BC/dqoZ3gL4yVUfQqd7JErQVDWChYUO0a9CYatpgXUHL5j0D5N+aJPgcTgyo8sCcxC WCWblgOFPg7064Ch3fhZlmbyjlTOtk2tedkHJU8uWQf2pHUNLrulAiWXIJ4ZhgFn4g7h JJTxypGlb6mni1HvAShrVnZgjNDkgG1R19guJgFQjaXNhzf27SS/2F5i4QwGEDN1xL87 pUOuWGwZ4z9LO34IpNGu77p8JcL961An0Ne7vwGy+q3KrL7Xr3Z+UXBowKStbgL7JRhr TkhESbRV2IxRKoUrw8yaSebooEeTmJxKUGZ0rWXgHDnjv3/UfvIa0I469ODS6mv8SalN XAKw== X-Forwarded-Encrypted: i=2; AKwUvBzXy/91+9TV5Rzx1v537iBYdaMHhm2jeEmeElBruKhh2HDqTozXfTe+tw80D2Y8y8zLXeJ5I/B8SyYIWk6z@patchwork.amarulasolutions.com X-Gm-Message-State: AFuF++mMftKvOHw6uH1TSWtQPbdu9UOBbdynmoQZt38kW+CF4LGy3B1E PEZqnZowAc6LM9H7ruAoflX1tEauOdEclGMMsRoOSTp3XqZp4WsE88Eoe+fcvhtZC/6+2g== X-Received: by 2002:a05:600c:3113:b0:49b:924e:9a28 with SMTP id 5b1f17b1804b1-49ce58163aemr221493275e9.1.1788449942620; Thu, 03 Sep 2026 08:39:02 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com; h="ATskLdetAgq2vwQruveNbdRRiYM4ZxeOPzxS3YgmRorUFK78nA==" Received: by 2002:a05:600c:1d01:b0:495:458f:eb16 with SMTP id 5b1f17b1804b1-49b21771792ls5463325e9.1.-pod-prod-05-eu; Thu, 03 Sep 2026 08:39:01 -0700 (PDT) X-Forwarded-Encrypted: i=2; AKwUvBwnYj5S6VMgKFV0SajvpesVQzVPFpa4Vp4sKb1L/B94FHDr3y1Utj+LSC5IS4eOjx1bvdZrRk0rtR3Db4Pe@amarulasolutions.com X-Received: by 2002:a05:600c:6296:b0:499:621a:2ec2 with SMTP id 5b1f17b1804b1-49ce581635bmr266505165e9.3.1788449940857; Thu, 03 Sep 2026 08:39:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1788449940; cv=none; d=google.com; s=arc-20260327; b=APV6nMi9fJ3RAOFIRyYGNvVClYAWJS81XfFSN5Ehn2zZgSYNoO2RQlpBHftmqobKc/ rnmzYc2V8YJS8gBXj2WLriMRIFprY/BbxOZyIiP0ksoWQgZTmeIINHUakRcOFf99pABV 5LDh16h/kJ1u/vQ2RFL3NLQ9aBv4orhxX9d+FP2FwuD1gpwk4R1AT9m3sVOm7aMMn+9A RdeKhxSLDpRyCcjmbewjjpExV0Z2+Z+nF+e+Gmf6gVW/2/s/m9ToBxLtWABvgvOK8rg1 eIzEf1zEEAeJAcomTPQKd2QZACnVKyNWFwvbYwQkv/ucCc41ov+Aeta9o3b7rb5j6Prm 2ryw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20260327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=cm4uXra2L9WOBsP9ackTlqi/Ub+9G7ZP+SENv4y3Q0o=; fh=3/gl2SXvHL2zPPV5cecDUeGHr2tCCP7FbSYSYL0ewS4=; b=nyQoXfuGIBQVK3Zev5RSBCQeHSxr391ZIQf4jkBtdQfGYpVd+uK/NbJEJGxT40sZ7r 8NlfIqNARsk1xDtNttaJTx25ZVdXg7rtCYYdZRLtk7aWvDefHHvZk4vsYYQFfjDyZy89 0CrCmYL7tsnSk7Xl5kczMFlLOp4TLxeyNoFo8UZXWwap6M4w8xuX0ewR2oXAvDU0z3dj bcJVh+pzAQwe6kwGS+Z7Syzz0Hnrv9KXwzOYtFrEDlKmyxkfK0ag1/15QH9YRv/8vwne l88yq4xiuye+3rIFAW5TuJNihG9b4gwUmfeQaQFOBO5POe7JKTTs8yIGyubCCjELQVic cBAw==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=llI208DO; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id ffacd0b85a97d-48448ed578fsor1044901f8f.13.2026.09.03.08.39.00 for (Google Transport Security); Thu, 03 Sep 2026 08:39:00 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AKwUvByKCnDumrSF00XLzoX1HN6lSRHH30JhkwUoBZudoLcHR/cp007Ci0kzwXD6YMsd2mCPvUReTGtjsMf8YLXq@amarulasolutions.com X-Gm-Gg: AYBFou3Y40i+cSgnkDselVjRXgJ6jz2FH4qrldh0nI0pNuWTyYjhknB7r7JK+QiXs3K qGNSaxzzKT/3VdJ9H7Dtt11paRBVkY5IJ3lUbdo+A047pm6p7Y0t8nD9Zi+BZqJshKH9tkF+ZHv aT/aYMGj777fD7FXy0COueRtoHQyFJ0np/4TUqflMhnQJA+jJsFYxJIDW60Y/+JA4w1P90+f4Ux ZctorGTUDB7r0/wkGm+RMMzZdzzZa+zJPmq/WEp7MV5RlAsJ+sR+5WjPbt2Htwni1QMx9rgkaNC Dv46Htqmc4H95fJ18GZDF4GwX99HZS5lc930fg4VDRTKcytFpYlV1Q5VpF7mcsgmTW6vW+5TfNc fYxt0DQRT6rmPX/Y1NpUhu0hGGCFG4I2svjbXmBwjuBWY6FKx1hHS+fHSTym8KovIKZJIN6ZzJ+ 8IbssKuXI1zxfzJNmMpsmU6vCewrc7jbYnKcYcJwMwIFR9O3mkoovXVgEOAy1EcrDLSS7u29SeI kPZwZchOqKX6dpZJ7XSleVSX9REWFmgU1W+OKbrnJcioBeB+AkFLdUTl6z5AcrlAPl0zWc6H9V8 7PAs9TjUkzO8ffr2s2IpOebqHvAJviT9Kn13SEIkUgOfunkn2iUsmmVw0Fg2Du9rEC4= X-Received: by 2002:a05:6000:2210:b0:47f:ec8a:214f with SMTP id ffacd0b85a97d-48488f0f6c6mr22597779f8f.15.1788449940413; Thu, 03 Sep 2026 08:39:00 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com (host-95-245-93-90.retail.telecomitalia.it. [95.245.93.90]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448e72df2sm15366301f8f.1.2026.09.03.08.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2026 08:38:59 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Abel Vesa , Brian Masney , Fabio Estevam , Frank Li , Jerome Brunet , Peng Fan , Pengutronix Kernel Team , Sascha Hauer , Stephen Boyd , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v13 4/4] clk: imx: pll14xx: support spread spectrum clock generation Date: Thu, 3 Sep 2026 17:32:16 +0200 Message-ID: <20260903153836.373267-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260903153836.373267-1-dario.binacchi@amarulasolutions.com> References: <20260903153836.373267-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=llI208DO; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add support for spread spectrum clock (SSC) generation to the pll14xx driver. Tested on the video PLL of i.MX8MN and i.MX8MP based boards. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- (no changes since v12) Changes in v12: - Apply the SSC settings also from the set_spread_spectrum() callback to handle the case the clock framework skips set_rate() if the requested rate is unchanged. Changes in v11: - Drop the dt-bindings/clock/clock.h include and use the enum clk_ssc_method values from clk-provider.h, as clk-scmi-oem.c does. - Disable SSC and clear the modulation fields in SSCG_CTRL when no spread method is configured, so that a setup left enabled by the bootloader is not kept active. - Skip the SSC setup instead of dividing by zero when modfreq_hz is zero or mfr truncates to zero. - Reject mfr and mrr values that do not fit the MFREQ_CTL and MRAT_CTL register fields instead of letting FIELD_PREP silently truncate them. This also prevents the 10000 * mfr multiplication from overflowing. - Compute the mfr divisor in 64-bit arithmetic, as the 32-bit product could wrap with out of range modfreq_hz values. Changes in v10: - Drop 'Reviewed-by' tag of Peng Fan. - Adapt the driver to the new infrastructure. Implement the set_spread_spectrum() and get the modulation parameters from struct clk_spread_spectrum. Changes in v9: - Add 'Reviewed-by' tag of Peng Fan. drivers/clk/imx/clk-pll14xx.c | 99 +++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index b6f1cc9f5700..5b187101c558 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,8 @@ #define GNRL_CTL 0x0 #define DIV_CTL0 0x4 #define DIV_CTL1 0x8 +#define SSCG_CTRL 0xc + #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) #define CLKE_MASK BIT(11) @@ -33,6 +36,13 @@ #define KDIV_MASK GENMASK(15, 0) #define KDIV_MIN SHRT_MIN #define KDIV_MAX SHRT_MAX +#define SSCG_ENABLE BIT(31) +#define MFREQ_CTL_MASK GENMASK(19, 12) +#define MRAT_CTL_MASK GENMASK(9, 4) +#define SEL_PF_DOWN_SPREAD 0 +#define SEL_PF_UP_SPREAD 1 +#define SEL_PF_CENTER_SPREAD 2 +#define SEL_PF_MASK GENMASK(1, 0) #define LOCK_TIMEOUT_US 10000 @@ -44,6 +54,7 @@ struct clk_pll14xx { int rate_count; s16 delta_k; spinlock_t lock; + struct clk_spread_spectrum ss_conf; }; #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw) @@ -366,6 +377,58 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static void __clk_pll1443x_set_spread_spectrum(struct clk_hw *hw, + unsigned long parent_rate, + unsigned int pdiv, + unsigned int mdiv) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct clk_spread_spectrum *conf = &pll->ss_conf; + u32 sscg_ctrl, mfr, mrr, sel_pf; + + sscg_ctrl = readl_relaxed(pll->base + SSCG_CTRL); + sscg_ctrl &= ~(SSCG_ENABLE | MFREQ_CTL_MASK | MRAT_CTL_MASK | SEL_PF_MASK); + + switch (conf->method) { + case CLK_SPREAD_CENTER: + sel_pf = SEL_PF_CENTER_SPREAD; + break; + case CLK_SPREAD_UP: + sel_pf = SEL_PF_UP_SPREAD; + break; + case CLK_SPREAD_DOWN: + sel_pf = SEL_PF_DOWN_SPREAD; + break; + default: + /* No spread: disable modulation and clear any stale state */ + goto out; + } + + if (!conf->modfreq_hz || !parent_rate || !pdiv) + goto out; + + mfr = div64_u64(parent_rate, (u64)conf->modfreq_hz * pdiv * BIT(5)); + if (!mfr || mfr > FIELD_MAX(MFREQ_CTL_MASK)) { + pr_warn("%s: SSC disabled, modulation frequency (%u Hz) out of range\n", + clk_hw_get_name(hw), conf->modfreq_hz); + goto out; + } + + mrr = (conf->spread_bp * mdiv * BIT(6)) / (10000 * mfr); + if (!mrr || mrr > FIELD_MAX(MRAT_CTL_MASK)) { + pr_warn("%s: SSC disabled, spread (%u permyriad) out of range\n", + clk_hw_get_name(hw), conf->spread_bp); + goto out; + } + + sscg_ctrl |= SSCG_ENABLE | FIELD_PREP(MFREQ_CTL_MASK, mfr) | + FIELD_PREP(MRAT_CTL_MASK, mrr) | + FIELD_PREP(SEL_PF_MASK, sel_pf); + +out: + writel_relaxed(sscg_ctrl, pll->base + SSCG_CTRL); +} + static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { @@ -390,6 +453,9 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + __clk_pll1443x_set_spread_spectrum(hw, prate, rate.pdiv, + rate.mdiv); + spin_unlock_irqrestore(&pll->lock, flags); return 0; @@ -411,6 +477,8 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1); + __clk_pll1443x_set_spread_spectrum(hw, prate, rate.pdiv, rate.mdiv); + spin_unlock_irqrestore(&pll->lock, flags); /* @@ -437,6 +505,36 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate, return 0; } +static int clk_pll1443x_set_spread_spectrum(struct clk_hw *hw, + const struct clk_spread_spectrum *ss_conf) +{ + struct clk_pll14xx *pll = to_clk_pll14xx(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = parent ? clk_hw_get_rate(parent) : 0; + unsigned long flags; + u32 div_ctl0; + + spin_lock_irqsave(&pll->lock, flags); + + pll->ss_conf = *ss_conf; + + /* + * Apply the configuration to the hardware right away, using the + * current PLL dividers: the clock framework does not call set_rate() + * if the requested rate is unchanged, so relying on it would leave + * the SSC settings unapplied when the PLL is already at the target + * rate (e.g. configured by the bootloader). + */ + div_ctl0 = readl_relaxed(pll->base + DIV_CTL0); + __clk_pll1443x_set_spread_spectrum(hw, parent_rate, + FIELD_GET(PDIV_MASK, div_ctl0), + FIELD_GET(MDIV_MASK, div_ctl0)); + + spin_unlock_irqrestore(&pll->lock, flags); + + return 0; +} + static int clk_pll14xx_prepare(struct clk_hw *hw) { struct clk_pll14xx *pll = to_clk_pll14xx(hw); @@ -509,6 +607,7 @@ static const struct clk_ops clk_pll1443x_ops = { .recalc_rate = clk_pll14xx_recalc_rate, .determine_rate = clk_pll1443x_determine_rate, .set_rate = clk_pll1443x_set_rate, + .set_spread_spectrum = clk_pll1443x_set_spread_spectrum, }; struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,