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[209.85.220.65]) by mx.google.com with SMTPS id z1sor3178067pjn.1.2019.06.11.07.55.03 for (Google Transport Security); Tue, 11 Jun 2019 07:55:03 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:2430:: with SMTP id h45mr28194841pje.14.1560264903013; Tue, 11 Jun 2019 07:55:03 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.54.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:55:02 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 48/92] ram: rk3399: Compute stride for 2 channels Date: Tue, 11 Jun 2019 20:20:51 +0530 Message-Id: <20190611145135.21399-49-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=WnwtPCWu; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , stride value from sdram timings can be computed dynamically based on the determined capacity for the given channel. Right now these stride values are taken as part of sdram timings via dtsi, but it possible to use same timings dtsi for given frequency even though the configured board sdram do support single channel with different size by dynamically detect the stride value. Example, NanoPi NEO4 do have DDR3-1866, but with single channel and 1GB size with dynamic stride detection it is possible to use existing rk3399-sdram-ddr3-1866.dtsi whose stride, number of channels and capacity it support is d efferent. So, add initial support to calculate the stride value for 2 channels sdram, which is available by default on existing boards. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 72 ++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 1acf9efe9c..5985c37f08 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1185,8 +1185,76 @@ static int switch_to_phy_index1(struct dram_info *dram, return 0; } +static unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params) +{ + unsigned int stride = sdram_params->base.stride; + unsigned int channel, chinfo = 0; + unsigned int ch_cap[2] = {0, 0}; + u64 cap; + + for (channel = 0; channel < 2; channel++) { + unsigned int cs0_cap = 0; + unsigned int cs1_cap = 0; + struct sdram_cap_info *cap_info = + &sdram_params->ch[channel].cap_info; + + if (cap_info->col == 0) + continue; + + cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + + cap_info->bk + cap_info->bw - 20)); + if (cap_info->rank > 1) + cs1_cap = cs0_cap >> (cap_info->cs0_row + - cap_info->cs1_row); + if (cap_info->row_3_4) { + cs0_cap = cs0_cap * 3 / 4; + cs1_cap = cs1_cap * 3 / 4; + } + ch_cap[channel] = cs0_cap + cs1_cap; + chinfo |= 1 << channel; + } + + /* stride calculation for 2 channels, default gstride type is 256B */ + if (ch_cap[0] == ch_cap[1]) { + cap = ch_cap[0] + ch_cap[1]; + switch (cap) { + /* 512MB */ + case 512: + stride = 0; + break; + /* 1GB */ + case 1024: + stride = 0x5; + break; + /* + * 768MB + 768MB same as total 2GB memory + * useful space: 0-768MB 1GB-1792MB + */ + case 1536: + /* 2GB */ + case 2048: + stride = 0x9; + break; + /* 1536MB + 1536MB */ + case 3072: + stride = 0x11; + break; + /* 4GB */ + case 4096: + stride = 0xD; + break; + default: + printf("%s: Unable to calculate stride for ", __func__); + print_size((cap * (1 << 20)), " capacity\n"); + break; + } + } + + return stride; +} + static int sdram_init(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) + struct rk3399_sdram_params *sdram_params) { unsigned char dramtype = sdram_params->base.dramtype; unsigned int ddr_freq = sdram_params->base.ddr_freq; @@ -1235,6 +1303,8 @@ static int sdram_init(struct dram_info *dram, set_ddrconfig(chan, sdram_params, channel, sdram_params->ch[channel].cap_info.ddrconfig); } + + sdram_params->base.stride = calculate_stride(sdram_params); dram_all_config(dram, sdram_params); switch_to_phy_index1(dram, sdram_params);