[52/92] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
diff mbox series

Message ID 20190611145135.21399-53-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Add LPDDR4 support
Related show

Commit Message

Jagan Teki June 11, 2019, 2:50 p.m. UTC 
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.

Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.

Bootchain after and before this change are:

 TPL -> SPL -> U-Boot proper

 rkbin -> SPL -> U-Boot proper

This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 +
 1 file changed, 1 insertion(+)

Patch
diff mbox series 

diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
index 7d22528f49..eb0aca4758 100644
--- a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
@@ -4,3 +4,4 @@ 
  */
 
 #include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-ddr3-1866.dtsi"