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[209.85.220.65]) by mx.google.com with SMTPS id o8sor15781526plk.18.2019.06.11.07.55.19 for (Google Transport Security); Tue, 11 Jun 2019 07:55:19 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:624:: with SMTP id 33mr77404730plg.325.1560264918711; Tue, 11 Jun 2019 07:55:18 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.55.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:55:18 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 52/92] rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi Date: Tue, 11 Jun 2019 20:20:55 +0530 Message-Id: <20190611145135.21399-53-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=nDsuaL94; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board. Since sdram rk3399 support dynamic stride and rank detection it can able to detect 1GB ddr eventough the timings are meant for dual channel, 2GB size. Bootchain after and before this change are: TPL -> SPL -> U-Boot proper rkbin -> SPL -> U-Boot proper This certainly fix the second channel data training initialization since we have dynamic rank, stride where second channel capabilities are clear or memset to 0. Signed-off-by: Jagan Teki --- arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi index 7d22528f49..eb0aca4758 100644 --- a/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi @@ -4,3 +4,4 @@ */ #include "rk3399-nanopi4-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1866.dtsi"