[63/92] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
diff mbox series

Message ID 20190611145135.21399-64-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Add LPDDR4 support
Related show

Commit Message

Jagan Teki June 11, 2019, 2:51 p.m. UTC 
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.

So, configure the same in pctl_cfg for LPDDR4.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 7 +++++++
 1 file changed, 7 insertions(+)

Patch
diff mbox series 

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 1abeee7198..7d2359740c 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -579,6 +579,13 @@  static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
 	writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
 
+	if (sdram_params->base.dramtype == LPDDR4) {
+		writel(sdram_params->phy_regs.denali_phy[898],
+		       &denali_phy[898]);
+		writel(sdram_params->phy_regs.denali_phy[919],
+		       &denali_phy[919]);
+	}
+
 	dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 					     PWRUP_SREFRESH_EXIT;
 	clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);