From patchwork Tue Jun 11 14:51:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 522 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 719903F08A for ; Tue, 11 Jun 2019 16:56:34 +0200 (CEST) Received: by mail-pf1-f198.google.com with SMTP id d125sf9787197pfd.3 for ; Tue, 11 Jun 2019 07:56:34 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1560264993; cv=pass; d=google.com; s=arc-20160816; b=BtVcoitFTCauXNmbbpAtd5pJhgbXHLSly9ByFQCQKzsCBsSZsGjnBmq63ZwaoBd1F0 YFVtrUS7bGJQaY0g5pa5C6gMGGUJ/JtX8N1RXYNsjaJ4eJGyEwIhu1B0oKyHZ/b9DX7X KwKEMlbB7cA4/gA7ag/QkRTSCV171RJ1b7xsFOQTVpXH/LCL6vADA79cNxLKe0EytQ2H 7a7OlJ5RX3tVgSUCRviZTJWD65XzYnwgv1Dw0z/iRjmzU3OtGepuCILa8RQVTJkPBnDg nHxOHElTCEpUAwk2m1GHjQBepHmX9oHj1zEH5CvZyWiOA7l7BGMQx/hq9NzdQHJkLEPC +m9w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4IFuzytInjHdGsPJ/YMOr5rwZvqcUX3Hj5rCfyUpXgg=; b=RF+e4Mb0xlZS659M2Dt7M8JkacuEI9vQC/71vgZy7ydtpWBs3bN5b8Gj5LHi8Ammg/ FYgxgpeYWcSZhLHIrDYGhaYZqwn1gx0B1J1qNd0OdtwmpD6LkRfGPYXJoTuUCQFKi0qR YSt7C3QgQYVk0LFd6Dx96JMqXb3QhDpTZHyBSadOb3icUglaTBrpHlX/Y7AxtSkOLX0U gfX3tIeLU7HxDYITS5448FMPpuvwF6XfgGHSJ/scqbEoyyy3bn5wEtEN8tQU6wgYn2J6 mxnCUDKaS/jI+diD5T5Bk8r2MocXeAz6AcuYeZNDJGKOfK0g3p/o9RwgrvL+CDDsk62f 4hQg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=i4tr6oM5; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=4IFuzytInjHdGsPJ/YMOr5rwZvqcUX3Hj5rCfyUpXgg=; b=l02PQxKCnpJ5dlOkfPvF5BUGYjCQBIKRW8Y2GzCie3e0ZOiBEY41//0+6YMRyJp8rS wuVtrotCZLhuTf7hmHkHdVMoMyFtUvVJNPoZ5WSf3OIsIqLw5iC0b9DdgezF9wPOiYLQ oqEcF5GVKuAKUxNkLQ3YgDlsqqveXygRChkDg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=4IFuzytInjHdGsPJ/YMOr5rwZvqcUX3Hj5rCfyUpXgg=; b=pQSCCvbMixK0kt+oK0YU+/4vFsYr09CdiyojsOHEMiLohsnKgRoaoxg03LOCr4E6bm SZI3n+R+w2OwZOhmG18QCw3Dg2n655e3Ol3z985fGshQsUKAutozY9lfMCa1kDlSx0Rz wVDZyWGASJCZ2hnN5oF43eKUTEVaYxeTNewThlcNnFoK27egQyCmXaIKDkDiyM9XXIMm OJ1K5VC/owdRfkiEuinpHUAElEWmlcPML/6OLN170LpOig7VO3E8W8Q8iUHp1mB2D840 dq6JmmQYfOUI98Z4lgy0MAKeGpQy5geOk8Art+bowur3T2JSpaqs8YdWyPM2fqajH56y kgpQ== X-Gm-Message-State: APjAAAUhtDar6fU/s80k83agGN3euDCPpZ1aUUhuQgLFrIDMbwh3XS2e xmOMYKZxVvaiUv+cmgi5mYtqn1cj X-Google-Smtp-Source: APXvYqw0AMQPBc2mrdNqE7rnMCBU3988SFQQPlzj8auT8mlR8LpuLdzhGYGtllMsZe0NFapUZ0FAvg== X-Received: by 2002:a62:2ec4:: with SMTP id u187mr79524137pfu.84.1560264993180; Tue, 11 Jun 2019 07:56:33 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:90a:d0c2:: with SMTP id y2ls859994pjw.5.gmail; Tue, 11 Jun 2019 07:56:33 -0700 (PDT) X-Received: by 2002:a17:90a:d58d:: with SMTP id v13mr27235709pju.1.1560264992867; Tue, 11 Jun 2019 07:56:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560264992; cv=none; d=google.com; s=arc-20160816; b=c9pcatTSCA9O7FfP23k8Q5SYymdaKpY+/S/w7QNkDVKMssd/9QQsimx+iG7s57yh1+ lFt9P8p7RcOJ7xKj23OET04jvhSnaXh4xYer0JudnCEIOnhHa8WCtGSHd/njK8k5SR54 NegIO+g7NPUdMStvklQE+f9x7umwM0fZD0h18Fy2upEHucyCZW3AxgC/6PKC9ELq4ltn 6P20o+/lvuqCizEx6tRSjNA3OcQJMs/erfmPVnP8ZHPDoKCETI4SKMrIeBrLkrGdGG14 1cpeILpjihmNwsx2z8YawOf9Ef63ZOCCHycN+bHAx4SUBS06o/TCnx8HZGXxGKwXFbpk 6VIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8c4S0X3iJtmuWtriTLrvafldLxCMegBBSbIDtgfjMO4=; b=N5kMYF3OhNndQnd8dzXSwk4fGYIlFh7mUFfhX7BzKXlVI4I5zgZjCqTo2grNpMbomQ hnNnUgLtKh1XLd6AD4izvj2BnUGmdfwBpoShPkLZMFPyL8RKJyH3UHr1vugvJ/3Cboe0 u57IcSU+vmCfBKtXZRrbXHfcPzy0INe2av76Ic87yW6BSPl5GHGGVLSjsttTq4oQNo5h Eu72pebhijgXbLJRtQKi46e9KchIaznIGepDy2wPJhgehLX0+MOgtMoN4Ih98AuvMi1c 3qqaq2wjCd8AN6ogGaYqezzgnytSl6OHHYaoBXqTHumm9bOxcuqT+KCpZ8r7xm2bFWrj e/kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=i4tr6oM5; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id d5sor7489044plr.38.2019.06.11.07.56.32 for (Google Transport Security); Tue, 11 Jun 2019 07:56:32 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:e306:: with SMTP id cg6mr46243669plb.341.1560264992549; Tue, 11 Jun 2019 07:56:32 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.18]) by smtp.gmail.com with ESMTPSA id e9sm16206208pfn.154.2019.06.11.07.56.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 11 Jun 2019 07:56:32 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH 71/92] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings Date: Tue, 11 Jun 2019 20:21:14 +0530 Message-Id: <20190611145135.21399-72-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=i4tr6oM5; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 5db7cbe116..6385df5600 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -184,6 +184,33 @@ struct io_setting { }, }; +/** + * phy = 0, PHY boot freq + * phy = 1, PHY index 0 + * phy = 2, PHY index 1 + */ +static struct io_setting * +lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5) +{ + struct io_setting *io = NULL; + u32 n; + + for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) { + io = &lpddr4_io_setting[n]; + + if (io->mr5 != 0) { + if (io->mhz >= params->base.ddr_freq && + io->mr5 == mr5) + break; + } else { + if (io->mhz >= params->base.ddr_freq) + break; + } + } + + return io; +} + static void *get_ddrc0_con(struct dram_info *dram, u8 channel) { return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1; @@ -525,7 +552,7 @@ static int phy_io_config(const struct chan_info *chan, } static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) + const struct rk3399_sdram_params *sdram_params, u32 mr5) { u32 *denali_phy = chan->publ->denali_phy; @@ -534,19 +561,22 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + struct io_setting *io = NULL; u32 reg_value; if (sdram_params->base.dramtype == LPDDR4) { + io = lpddr4_get_io_settings(sdram_params, mr5); + tsel_rd_select_p = PHY_DRV_ODT_HI_Z; - tsel_rd_select_n = PHY_DRV_ODT_240; + tsel_rd_select_n = io->rd_odt; tsel_idle_select_p = PHY_DRV_ODT_HI_Z; tsel_idle_select_n = PHY_DRV_ODT_240; - tsel_wr_select_dq_p = PHY_DRV_ODT_40; + tsel_wr_select_dq_p = io->wr_dq_drv; tsel_wr_select_dq_n = PHY_DRV_ODT_40; - tsel_wr_select_ca_p = PHY_DRV_ODT_40; + tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; } else if (sdram_params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; @@ -728,7 +758,7 @@ static void pctl_start(struct dram_info *dram, } static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, - u32 channel, const struct rk3399_sdram_params *sdram_params) + u32 channel, struct rk3399_sdram_params *sdram_params) { u32 *denali_ctl = chan->pctl->denali_ctl; u32 *denali_pi = chan->pi->denali_pi; @@ -812,7 +842,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, sdram_params); + set_ds_odt(chan, sdram_params, 0); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8