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[209.85.220.65]) by mx.google.com with SMTPS id w11sor35701938pgs.5.2018.11.16.08.41.08 for (Google Transport Security); Fri, 16 Nov 2018 08:41:08 -0800 (PST) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:504d:: with SMTP id q13mr10719267pgl.319.1542386468336; Fri, 16 Nov 2018 08:41:08 -0800 (PST) Received: from localhost.localdomain ([115.97.190.86]) by smtp.gmail.com with ESMTPSA id p5-v6sm34622213pfb.109.2018.11.16.08.41.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Nov 2018 08:41:07 -0800 (PST) From: Jagan Teki To: Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Rob Herring , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Vasily Khoruzhick , Thierry Reding , Mark Rutland , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Michael Trimarchi , TL Lim , linux-sunxi@googlegroups.com, linux-amarula@amarulasolutions.com Cc: Jagan Teki Subject: [PATCH v2 12/12][DO NOT MERGE] arm64: allwinner: a64: pine64-lts: Enable Feiyang FY07024DI26A30-D DSI panel Date: Fri, 16 Nov 2018 22:09:16 +0530 Message-Id: <20181116163916.29621-13-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20181116163916.29621-1-jagan@amarulasolutions.com> References: <20181116163916.29621-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=PfiaEhEO; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Feiyang FY07024DI26A30-D MIPI_DSI panel is desiged to attach with DSI connector on pine64 boards, enable the same for pine64 LTS. DSI panel connected via board DSI port with, - DC1SW as AVDD supply - DLDO2 as DVDD supply - DLDO1 as VCC-DSI supply - PD24 gpio for reset pin - PH10 gpio for backlight enable pin Signed-off-by: Jagan Teki --- .../dts/allwinner/sun50i-a64-pine64-lts.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts index 72d6961dc312..9e230c612799 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts @@ -5,9 +5,46 @@ */ #include "sun50i-a64-sopine-baseboard.dts" +#include / { model = "Pine64 LTS"; compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", "allwinner,sun50i-a64"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <1 2 4 8 16 32 64 128 512>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* LCD-BL-EN: PH10 */ + }; +}; + +&de { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi { + vcc-dsi-supply = <®_dldo1>; /* VCC3V3-DSI */ + status = "okay"; + + panel@0 { + compatible = "feiyang,fy07024di26a30d"; + reg = <0>; + avdd-supply = <®_dc1sw>; /* VCC-LCD */ + dvdd-supply = <®_dldo2>; /* VCC-MIPI */ + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ + backlight = <&backlight>; + }; +}; + +&r_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&r_pwm_pin>; + status = "okay"; };