From patchwork Mon Jun 17 07:32:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 645 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id EB9613F353 for ; Mon, 17 Jun 2019 09:40:28 +0200 (CEST) Received: by mail-pf1-f200.google.com with SMTP id c17sf6544200pfb.21 for ; Mon, 17 Jun 2019 00:40:28 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1560757227; cv=pass; d=google.com; s=arc-20160816; b=Blr4shtljSaqOlFz2nMS1n7Fymjzbd/KI58Ys3/Cadw0uP4fuFhzTfeVkNSUL9E2/P 2tV1tv7qr0nuWJKHEbdpfMqtognicuFdR6B4bnK7DEwvipuYigcniBAy17PXUe3MfRsF 6s1IhVMtKwk5dkz/OBOHEpIiCgYvx6vZ4HZya7pEeunm4PjG5HCZNhmAjx46sTiix6e+ jksbZ4JnW32/3v+nMyabn2ellsxBEgD8L91nckfkIJuvlolNR4QcjZQy7NNuENOipAGK g9wTHSIaluB5lTgHBN3jZ9OUH0FuZCPtPhWTVAX0j33Om0F5z6c9PvMnQc9k2JjEUq2N lPVQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0mcK88ZsQxA0WGYTxKkhQJu9GmaGEg7WGtpGN6L4wa4=; b=txqxttiiMXCqK0QTd6Dy9orYbgyxMkcHghxMccwoX/ALSkdOeKydPhI/P08NigOlg0 eiRzAFbQIS4zk1p6AaexP+bwC8tLv8X0/saZMsoEWT91ozLueT87ajWFPwLxtaMGl+fz xK700pPrkPyCt4MyFuHm4gdPc2X+Ci0xB9cKnovUcbs/VIpnmNw72bo/+lHj7NEq4Kn0 ZD9fRDiRl4hWBRdIKUjIFKGe6nB40fBn3CSr1jaAruTZCDDWkVxSZZORF95yAh1f8O7K YsmFeXCjbWVAktfVtxD4Io9t1CvqlktXVZWj7pxCfm8f3lIcN8ArUeASc0+b0WCZ9nT2 VfNQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TFnHI2pv; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=0mcK88ZsQxA0WGYTxKkhQJu9GmaGEg7WGtpGN6L4wa4=; b=j8HoID9h1DtcJSlVruZbjgU+jItTEC5zw9KdfBU1cd2RPHkk0UDhFX0/rzwkI+UyVe DSD4KZqvCelyATwQBDpX5PPTl2trbEj4ODnoKFQK9n+3GCsCbIt3Qf07st19uaIkUGqx 5dz1YFFlep7qL4BsoCjG3tKmOW0itypwAWEWk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=0mcK88ZsQxA0WGYTxKkhQJu9GmaGEg7WGtpGN6L4wa4=; b=qb/sXJ1fRhIeBEoEJe9v0wv+tRO579tAGH7U9R/v1hfZJckLg4Pqrb0t8uXbTTns6g Qv2hbRDv+IdBbU45ptPZnwZZvpsxZWGUvmIbFhd5nmeW8DTJ5Y+hOvl9Z32xXjuvoZ6Q ErH9h5VfNnvK4OqZCI6Wm3WT38lHCYJSHwuKXlFkMg1EfgaxpemHlrHoJOLcJYT18lLg boyN1GAqF0/UokxJSeabDD5A0RI0drFCUdhmKFzcHZBkwQa8vDhaQCQa0cT1n7dlv8JF 7ILf+Q9LuRCgFE6WAAa5quhmHLQ38ayMymDU0HyWYWLt7MrMd3ahgFNuQdukE4LJCRO2 Pu7w== X-Gm-Message-State: APjAAAVnw+kGv1SmD7eC8dYycoQ8TuejctEKuKLNQgr4AK3OEOIiLuxB BXaHwUA9NJHr9IjQWlNyOF8P2/+G X-Google-Smtp-Source: APXvYqygAxdawMdRZYif3cgZqFYHiwcN+j5x4O0Xfnxr3hF55nAUThPk1ubu2AG7Zv0RcHFdKS+iyw== X-Received: by 2002:a17:902:724:: with SMTP id 33mr104077946pli.49.1560757227786; Mon, 17 Jun 2019 00:40:27 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a63:c015:: with SMTP id h21ls3591075pgg.3.gmail; Mon, 17 Jun 2019 00:40:27 -0700 (PDT) X-Received: by 2002:a63:50a:: with SMTP id 10mr49072388pgf.213.1560757227354; Mon, 17 Jun 2019 00:40:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560757227; cv=none; d=google.com; s=arc-20160816; b=Uc4JyPdX7tJKLt2kvaM1Yy+m9gkB+u4Tq9MrDEL82DpuZ3RmzhGSbHxxCQEYpKUDhn 1oyX3eMKq3J6U7NIbqLreFnDr+3RIdpPRSUlDV7xXMcxlwV602wRjLRxx0sBlGeF5GRz rwKeVRWj0ww3bMl5YoYOe0+tMxdaMLZSmVmmQTtVaDcH5V25A/WDMHjzOGT7HbNhi8Xc arwQ5fXjVl5q5SI1l+EY7fvXibntVnm+7N9bL+83BVIZ8/sD783u3VGzVSxMsebOYGsf Dq3XxcThwGtPOf5EG99nz6V/pjbtQ519Q+CB4LYxqJgIf2ITPXZ505Ta/3r8rgStCm6b ounQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=I8k1428OrKZlOFrLY3vjmLkceYCA5xz8iJB5tOTiA78=; b=i3nXEP8DR8DWdbm1W1pipsKSFMoh0/NDdsLuxD4OM78bbwSCvLmkYAz5MV9dkZkc9E k1oraFDnwDDJE4IAZGQGo8/7Q3z6nKbB3M1oKJDdAedFYmEFB3lSJ24xd31BN76bRPvd xAqRpzC32ck4hmoalUpMGkxHByidf3UKBKTW1KGZWG2T9FLNHX+zPijHpqB4Czeidhsp fIm0V7P/ayGmqjBwPSQKESKV+j6JptqUo78JoQlDq7PexFbQ3XlftaeOgxP1tgK/yOza augocZ0zGnX1Mo1E00Mf7Bxt1DBjm3OMuWFwHc4SRrSEpvGYeBy4UaUK18b7gpSxnwKM nHyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TFnHI2pv; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id k6sor4721255pgs.79.2019.06.17.00.40.27 for (Google Transport Security); Mon, 17 Jun 2019 00:40:27 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a63:2e02:: with SMTP id u2mr154312pgu.112.1560757226987; Mon, 17 Jun 2019 00:40:26 -0700 (PDT) Received: from localhost.localdomain ([49.206.203.245]) by smtp.gmail.com with ESMTPSA id m41sm15205998pje.18.2019.06.17.00.40.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jun 2019 00:40:26 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: Manivannan Sadhasivam , gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v2 74/99] ram: rk3399: Add tsel control clock drive Date: Mon, 17 Jun 2019 13:02:27 +0530 Message-Id: <20190617073252.27810-75-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190617073252.27810-1-jagan@amarulasolutions.com> References: <20190617073252.27810-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=TFnHI2pv; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 22c1a66185..caf8180018 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + u32 tsel_ckcs_select_p, tsel_ckcs_select_n; struct io_setting *io = NULL; u32 reg_value; @@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; + + tsel_ckcs_select_p = io->wr_ckcs_drv; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_wr_select_ca_n = PHY_DRV_ODT_48; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } if (params->base.odt == 1) @@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits_le32(&denali_phy[939], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits_le32(&denali_phy[929], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff,