new file mode 100644
@@ -0,0 +1,9 @@
+$(call force,CFG_ARM32_core,y)
+$(call force,CFG_ARM64_core,n)
+$(call force,CFG_HWSUPP_MEM_PERM_WXN,y)
+$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
+arm32-platform-cpuarch := cortex-a17
+arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch)
+arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch)
+# Program flow prediction may need manual enablement
+CFG_ENABLE_SCTLR_Z ?= y
@@ -5,6 +5,12 @@ include ./core/arch/arm/cpu/cortex-a7.mk
$(call force,CFG_TEE_CORE_NB_CORE,4)
endif
+ifeq ($(PLATFORM_FLAVOR),rk3288vyasa)
+include ./core/arch/arm/cpu/cortex-a17.mk
+$(call force,CFG_TEE_CORE_NB_CORE,4)
+endif
+
+
$(call force,CFG_GENERIC_BOOT,y)
$(call force,CFG_GIC,y)
$(call force,CFG_HWSUPP_MEM_PERM_PXN,y)
@@ -31,8 +31,10 @@
#include <common.h>
#include <platform_config.h>
+#include <platform_rk3288.h>
-#if defined(PLATFORM_FLAVOR_rk322x)
+
+#if defined(PLATFORM_FLAVOR_rk322x) || defined(PLATFORM_FLAVOR_rk3288vyasa)
enum plls_id {
APLL_ID,
@@ -34,6 +34,7 @@
#include <kernel/panic.h>
#include <kernel/pm_stubs.h>
#include <mm/core_memprot.h>
+#include <platform_rk3288.h>
#include <platform_config.h>
#include <stdint.h>
#include <tee/entry_std.h>
@@ -30,9 +30,10 @@
#include <io.h>
#include <mm/core_memprot.h>
#include <platform_config.h>
+#include <platform_rk3288.h>
#include <stdint.h>
-#if defined(PLATFORM_FLAVOR_rk322x)
+#if defined(PLATFORM_FLAVOR_rk322x) || defined(PLATFORM_FLAVOR_rk3288vyasa)
#define SGRF_SOC_CON(n) ((n) * 4)
#define DDR_SGRF_DDR_CON(n) ((n) * 4)
@@ -55,6 +55,9 @@
#define PERIPH_BASE 0x10100000
#define PERIPH_SIZE 0x22000000
+#elif defined(PLATFORM_FLAVOR_rk3288vyasa)
+#include <platform_rk3288.h>
+
#else
#error "Unknown platform flavor"
#endif
@@ -94,4 +97,6 @@
#define MAX_XLAT_TABLES 5
#endif
+
#endif
+
new file mode 100644
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (C) 2018, Amarula Solutions
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define GIC_BASE 0xffc01000
+#define GICC_OFFSET 0x0000
+#define GICD_OFFSET 0x1000
+
+#define GICC_BASE (GIC_BASE + GICC_OFFSET)
+#define GICD_BASE (GIC_BASE + GICD_OFFSET)
+
+#define SGRF_BASE 0xff740000
+#define DDRSGRF_BASE 0x10150000
+#define GRF_BASE 0xff770000
+#define UART2_BASE 0xff690000
+#define CRU_BASE 0xff760000
+
+/* Internal SRAM */
+#define ISRAM_BASE 0xff720000
+#define ISRAM_SIZE 0x8000
+
+/* Periph IO */
+#define PERIPH_BASE 0x10100000
+#define PERIPH_SIZE 0x22000000
+
+#define CONSOLE_UART_BASE UART2_BASE
+#define CONSOLE_BAUDRATE 1500000
+#define CONSOLE_UART_CLK_IN_HZ 24000000
+
+/*
+ * Rockchip memory map
+ *
+ * +---------------------------+
+ * | | TEE_RAM | 1 MiB |
+ * + TZDRAM +------------------+
+ * | | TA_RAM | 1 MiB |
+ * +--------+---------+--------+
+ * | SHMEM | | 1 MiB |
+ * +---------------------------+
+ */
+#define TEE_RAM_PH_SIZE TEE_RAM_VA_SIZE
+#define TEE_RAM_START TZDRAM_BASE
+#define TEE_RAM_VA_SIZE (1024 * 1024)
+#define TEE_RAM_SIZE TEE_RAM_VA_SIZE
+
+#define TA_RAM_START (TEE_RAM_START + TEE_RAM_SIZE)
+#define TA_RAM_SIZE (1024 * 1024)
+#define TEE_SHMEM_START (TA_RAM_START + TA_RAM_SIZE)
+#define TEE_SHMEM_SIZE (1024 * 1024)
+
+/* Location of trusted dram */
+#define TZDRAM_BASE 0x68400000
+#define TZDRAM_SIZE (TEE_RAM_SIZE + TA_RAM_SIZE)
+
+#define TEE_LOAD_ADDR TZDRAM_BASE
+
+#ifdef CFG_WITH_LPAE
+#define MAX_XLAT_TABLES 5
+#endif
@@ -39,6 +39,7 @@
#include <mm/core_mmu.h>
#include <mm/core_memprot.h>
#include <platform_config.h>
+#include <platform_rk3288.h>
#include <sm/optee_smc.h>
#include <sm/psci.h>
#include <stdint.h>