From patchwork Sun Oct 7 12:13:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shyam Saini X-Patchwork-Id: 7 X-Patchwork-Delegate: shyam.saini@amarulasolutions.com Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pf1-f197.google.com (cartago.priv [10.11.12.1]) by cassiopea (Postfix) with ESMTPS id 24DFB2E2B0E for ; Sun, 7 Oct 2018 14:14:22 +0200 (CEST) Received: by mail-pf1-f197.google.com with SMTP id 14-v6sf12036989pfk.22 for ; Sun, 07 Oct 2018 05:14:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1538914460; cv=pass; d=google.com; s=arc-20160816; b=ZZTNC4TMFWbW0uEqSohHwcLmmd6Bjb487EkDQm/PXVxR5M7FoH53YIO06rVt5kfwbH gUpIaUvKIyHkR0sXMRyK18VMDRMZqcdj9N9zTTa9SLlinaezEk7KJhMKt/Ss0nBXbXPp axBdLTr71l9e+4b6TP0q3t8YzAROSNtQYXC70hqsQYaW0+1Ksigcx0wrq7TrjI5ANqYc 5JwD2BRb4msA+GjoJTwGHUzKRcEgMJfNVvkVmCLNzdakW/B2/5w/jpxSA2y463IrbHh9 xs+tXgq9YoEd1uyBa/8CNjWX9gvckXNh45fjGs3EDJzHbZYHuV6vRckAycYT/Hghd3wy XUVA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:message-id:date:subject:cc:to:from :mime-version:dkim-signature; bh=Kia5OYZME3yXyZukNSY+y/SC0TEovOEVN0KiN8PXkPg=; b=ZayBBHrzH6XUynn0dvmIOXEi+KxHgjq55Cwi2MHPkrMfjOVugiuFrXgvpSZC+X5LNP ZrhJbRfWZRYiSPtVej6e/ka4hnflGm/0SnOpjKhhTf0FA8qJNJL/XHcotMnIrkDCLPaU jJaAQDizaCAwMtKPh0ZoYfUdZOe6dgzfkc3HlCyAFGJnCSElADkhc0KHfGfIaA/OC9pG X2Vz95fCM6+22Es6hFAUwsiZRwf55ZOSJl+ASYGItYoifRapyH3ZkddJ3Vs6NcGqsY4j Azb0jfm9+/HWXXSEQwbmJPFDk+F0InNSJ1uhSpxgysyqM7wcRWY7Ki9+R3YQsERORWdN yDGw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=H8jSfyXq; spf=pass (google.com: domain of shyam.saini@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=shyam.saini@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=mime-version:from:to:cc:subject:date:message-id:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=Kia5OYZME3yXyZukNSY+y/SC0TEovOEVN0KiN8PXkPg=; b=RDgjqMOHnMiffgWWDU5zd5M+UhYte34YiFT+zBoRdHwoN26h5IRZ9YALvJvcWdSk/j 5zf2g0XbPn6gl00enGyw82BKla3kqY+aZVum5qJeyGNPKH9RGeo65HTncdqh7OklpgLo xRESnQg1whS5eNT4gp4ImViSIWB6dWgukXkVw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:to:cc:subject:date:message-id :x-original-sender:x-original-authentication-results:precedence :mailing-list:list-id:x-spam-checked-in-group:list-post:list-help :list-archive:list-unsubscribe; bh=Kia5OYZME3yXyZukNSY+y/SC0TEovOEVN0KiN8PXkPg=; b=HYK9LKW3Dd3M0R1yPKBv4hp036hpm2tKD3qDtefgtMWu5aW/doLJtUYG6jsqSF0/2A 6QdaAB6NtT50X4zpPxlyeJgxBN71etIas+ctkJ3nr//YWVhC7h4Vd+XAGdGhc9mbuq5X xGwzCnDS2RxyhpPStfiF11SJedaeQAdYXcHh3aVtBfZE/+mVoLwQBORZi/7CxAMHcUuH 3Z03kj8r1/JwAXdR87/eCsRjbDBswL/UODDFFw+yFWgFfJWJtyu6+ej1bYfnLXaOlWDt FmHKEOh1GOUVOtTLc4d8Ate2YajlsPHpRWsYHfmFdf/IUD7b/IHCzTv8kfaZQ+oF0lsi XUAA== X-Gm-Message-State: ABuFfoj5vVjxYp/CS7QFSTDk6ekpCt5DQ0UJuhBnPY8aDKRURdOcC5OV sd3sGaN+//2f/jPBiI9CJMmQhsC+ X-Google-Smtp-Source: ACcGV61DCee6a6p6UVWh/iiccod+1ZTzuuBt5rKsVgBbqGbYK6lK+t8l6l8yYrYHY7Hoejfo4vg4YA== X-Received: by 2002:a17:902:830b:: with SMTP id bd11-v6mr9561849plb.8.1538914459906; Sun, 07 Oct 2018 05:14:19 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:8e8a:: with SMTP id bg10-v6ls5298982plb.4.gmail; Sun, 07 Oct 2018 05:14:19 -0700 (PDT) X-Received: by 2002:a17:902:124:: with SMTP id 33-v6mr19773045plb.205.1538914459373; Sun, 07 Oct 2018 05:14:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1538914459; cv=none; d=google.com; s=arc-20160816; b=DfpJlaCmEaRyOuIkVmgpKD+LWLjmdRqqttLo3ETAfAFnY6bKP+1jCoczkY+7jqUakp cMCtC6Y4d9J1e1TfVk7cJEmzhZsWn0RP+Q8oDiNwsCbYqPlOV/3394u5k8+27w/ssJjV S3LlfKQQDfLXDLk4qM78pY+fnXYNGjS4dzvJUotFh/60GAy/bhJILGGXgcVY2Geb1nFz xGemoewD514GxX2SPW2pYNdxHAwc68nDcmn2zqTRqj4zNAW7Cvg2amefjsX6JuBZ72wa 0ZmOhbfrh958eaH09Dzxk5+ZlX/JUIGUdIKCGg/H5MZ/Bg6DdPKtV1fvAcH1HRkVY07R QA/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:dkim-signature; bh=Kia5OYZME3yXyZukNSY+y/SC0TEovOEVN0KiN8PXkPg=; b=nzmuSrCtu5F+yBwAxevOK9nPdtdNA3wrkYv9fg+q2r/4WC/uF8DbhEJeU3//g632p8 P3DX+sr0RqOtgIvEVZzaTqMJGp1xs50EuaWGT7AhhNY1rN337VaaX5EW4+B6y/Aemx2H aXpOHBBTcBgRnQyG+h+1R8uDxLNrJ7TGyBVHsn2F7qWDJAnsrsz4S5EYIqrJGA4m3xMa TqQG+esBGCYfSXc/XGZgNQbLW9AkRskbg/Xi1QAZr98XL3+8+lcXQ7ChCY+PfqnEiM1Y I11opNy2YR3eOimB5eFYRS0+JwBDgj52CNMxA+AY6cpDiQviByPDM5yTHFHBjr3xQ591 c7Vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=H8jSfyXq; spf=pass (google.com: domain of shyam.saini@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=shyam.saini@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id f27-v6sor11120825pfe.5.2018.10.07.05.14.19 for (Google Transport Security); Sun, 07 Oct 2018 05:14:19 -0700 (PDT) Received-SPF: pass (google.com: domain of shyam.saini@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a62:48ce:: with SMTP id q75-v6mr20881424pfi.22.1538914458019; Sun, 07 Oct 2018 05:14:18 -0700 (PDT) Received: from localhost.localdomain ([42.111.25.240]) by smtp.gmail.com with ESMTPSA id o24-v6sm21323792pfa.90.2018.10.07.05.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Oct 2018 05:14:17 -0700 (PDT) From: Shyam Saini To: linux-amarula@amarulasolutions.com Cc: Shyam Saini Subject: [PATCH] core: plat-rockchip: Add initial support for rk3288 soc Date: Sun, 7 Oct 2018 17:43:56 +0530 Message-Id: <20181007121356.26358-1-shyam.saini@amarulasolutions.com> X-Mailer: git-send-email 2.11.0 X-Original-Sender: shyam.saini@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=H8jSfyXq; spf=pass (google.com: domain of shyam.saini@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=shyam.saini@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Shyam Saini These changes are adopted from already existing rk32xx support. To test this support, follow below mentioned steps: [1] $ git clone optee repo from https://github.com/OP-TEE/optee_os [2] $ export CROSS_COMPILE=arm-linux-gnueabi- [3] $ export PATH=~/gcc-linaro-6.3.1-2017.02-i686_arm-linux-gnueabi/bin:$PATH [4] $ make PLATFORM=rockchip PLATFORM_FLAVOR=rk3288vyasa On successfull compilation, you can find tee image here out/arm-plat-rockchip/core/tee.elf Signed-off-by: Shyam Saini --- core/arch/arm/cpu/cortex-a17.mk | 9 +++ core/arch/arm/plat-rockchip/conf.mk | 6 ++ core/arch/arm/plat-rockchip/cru.h | 4 +- core/arch/arm/plat-rockchip/main.c | 1 + core/arch/arm/plat-rockchip/platform.c | 3 +- core/arch/arm/plat-rockchip/platform_config.h | 5 ++ core/arch/arm/plat-rockchip/platform_rk3288.h | 83 +++++++++++++++++++++++++++ core/arch/arm/plat-rockchip/psci_rk322x.c | 1 + 8 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 core/arch/arm/cpu/cortex-a17.mk create mode 100644 core/arch/arm/plat-rockchip/platform_rk3288.h diff --git a/core/arch/arm/cpu/cortex-a17.mk b/core/arch/arm/cpu/cortex-a17.mk new file mode 100644 index 000000000000..31aaad91ae57 --- /dev/null +++ b/core/arch/arm/cpu/cortex-a17.mk @@ -0,0 +1,9 @@ +$(call force,CFG_ARM32_core,y) +$(call force,CFG_ARM64_core,n) +$(call force,CFG_HWSUPP_MEM_PERM_WXN,y) +$(call force,CFG_HWSUPP_MEM_PERM_PXN,y) +arm32-platform-cpuarch := cortex-a17 +arm32-platform-cflags += -mcpu=$(arm32-platform-cpuarch) +arm32-platform-aflags += -mcpu=$(arm32-platform-cpuarch) +# Program flow prediction may need manual enablement +CFG_ENABLE_SCTLR_Z ?= y diff --git a/core/arch/arm/plat-rockchip/conf.mk b/core/arch/arm/plat-rockchip/conf.mk index 5de3b818120a..48a16d39c4a3 100644 --- a/core/arch/arm/plat-rockchip/conf.mk +++ b/core/arch/arm/plat-rockchip/conf.mk @@ -5,6 +5,12 @@ include ./core/arch/arm/cpu/cortex-a7.mk $(call force,CFG_TEE_CORE_NB_CORE,4) endif +ifeq ($(PLATFORM_FLAVOR),rk3288vyasa) +include ./core/arch/arm/cpu/cortex-a17.mk +$(call force,CFG_TEE_CORE_NB_CORE,4) +endif + + $(call force,CFG_GENERIC_BOOT,y) $(call force,CFG_GIC,y) $(call force,CFG_HWSUPP_MEM_PERM_PXN,y) diff --git a/core/arch/arm/plat-rockchip/cru.h b/core/arch/arm/plat-rockchip/cru.h index 73792a919a87..12efdf453e22 100644 --- a/core/arch/arm/plat-rockchip/cru.h +++ b/core/arch/arm/plat-rockchip/cru.h @@ -31,8 +31,10 @@ #include #include +#include -#if defined(PLATFORM_FLAVOR_rk322x) + +#if defined(PLATFORM_FLAVOR_rk322x) || defined(PLATFORM_FLAVOR_rk3288vyasa) enum plls_id { APLL_ID, diff --git a/core/arch/arm/plat-rockchip/main.c b/core/arch/arm/plat-rockchip/main.c index 7d1fda38b3b6..3f8c0d580d00 100644 --- a/core/arch/arm/plat-rockchip/main.c +++ b/core/arch/arm/plat-rockchip/main.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/core/arch/arm/plat-rockchip/platform.c b/core/arch/arm/plat-rockchip/platform.c index fdf50d760ab9..9049c02613bf 100644 --- a/core/arch/arm/plat-rockchip/platform.c +++ b/core/arch/arm/plat-rockchip/platform.c @@ -30,9 +30,10 @@ #include #include #include +#include #include -#if defined(PLATFORM_FLAVOR_rk322x) +#if defined(PLATFORM_FLAVOR_rk322x) || defined(PLATFORM_FLAVOR_rk3288vyasa) #define SGRF_SOC_CON(n) ((n) * 4) #define DDR_SGRF_DDR_CON(n) ((n) * 4) diff --git a/core/arch/arm/plat-rockchip/platform_config.h b/core/arch/arm/plat-rockchip/platform_config.h index 01a758a987e7..968250ba5fb1 100644 --- a/core/arch/arm/plat-rockchip/platform_config.h +++ b/core/arch/arm/plat-rockchip/platform_config.h @@ -55,6 +55,9 @@ #define PERIPH_BASE 0x10100000 #define PERIPH_SIZE 0x22000000 +#elif defined(PLATFORM_FLAVOR_rk3288vyasa) +#include + #else #error "Unknown platform flavor" #endif @@ -94,4 +97,6 @@ #define MAX_XLAT_TABLES 5 #endif + #endif + diff --git a/core/arch/arm/plat-rockchip/platform_rk3288.h b/core/arch/arm/plat-rockchip/platform_rk3288.h new file mode 100644 index 000000000000..bf3343942e0f --- /dev/null +++ b/core/arch/arm/plat-rockchip/platform_rk3288.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2018, Amarula Solutions + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#define GIC_BASE 0xffc01000 +#define GICC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 + +#define GICC_BASE (GIC_BASE + GICC_OFFSET) +#define GICD_BASE (GIC_BASE + GICD_OFFSET) + +#define SGRF_BASE 0xff740000 +#define DDRSGRF_BASE 0x10150000 +#define GRF_BASE 0xff770000 +#define UART2_BASE 0xff690000 +#define CRU_BASE 0xff760000 + +/* Internal SRAM */ +#define ISRAM_BASE 0xff720000 +#define ISRAM_SIZE 0x8000 + +/* Periph IO */ +#define PERIPH_BASE 0x10100000 +#define PERIPH_SIZE 0x22000000 + +#define CONSOLE_UART_BASE UART2_BASE +#define CONSOLE_BAUDRATE 1500000 +#define CONSOLE_UART_CLK_IN_HZ 24000000 + +/* + * Rockchip memory map + * + * +---------------------------+ + * | | TEE_RAM | 1 MiB | + * + TZDRAM +------------------+ + * | | TA_RAM | 1 MiB | + * +--------+---------+--------+ + * | SHMEM | | 1 MiB | + * +---------------------------+ + */ +#define TEE_RAM_PH_SIZE TEE_RAM_VA_SIZE +#define TEE_RAM_START TZDRAM_BASE +#define TEE_RAM_VA_SIZE (1024 * 1024) +#define TEE_RAM_SIZE TEE_RAM_VA_SIZE + +#define TA_RAM_START (TEE_RAM_START + TEE_RAM_SIZE) +#define TA_RAM_SIZE (1024 * 1024) +#define TEE_SHMEM_START (TA_RAM_START + TA_RAM_SIZE) +#define TEE_SHMEM_SIZE (1024 * 1024) + +/* Location of trusted dram */ +#define TZDRAM_BASE 0x68400000 +#define TZDRAM_SIZE (TEE_RAM_SIZE + TA_RAM_SIZE) + +#define TEE_LOAD_ADDR TZDRAM_BASE + +#ifdef CFG_WITH_LPAE +#define MAX_XLAT_TABLES 5 +#endif diff --git a/core/arch/arm/plat-rockchip/psci_rk322x.c b/core/arch/arm/plat-rockchip/psci_rk322x.c index 3e6e72b3e2f6..a2266552c757 100644 --- a/core/arch/arm/plat-rockchip/psci_rk322x.c +++ b/core/arch/arm/plat-rockchip/psci_rk322x.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include