| Message ID | 20190715182856.21688-6-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
|
| Related | show |
On 2019/7/16 上午2:28, Jagan Teki wrote: > Add support for phy pctrl reset support for both channel 0, 1. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/ram/rockchip/sdram_rk3399.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 16bd9427a6..a5da985e1a 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -35,6 +35,10 @@ > #define PHY_DRV_ODT_40 0xe > #define PHY_DRV_ODT_34_3 0xf > > +#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ > + ((n) << (8 + (ch) * 4))) > +#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ > + ((n) << (9 + (ch) * 4))) > struct chan_info { > struct rk3399_ddr_pctl_regs *pctl; > struct rk3399_ddr_pi_regs *pi; > @@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) > } > } > > +static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, > + u32 phy) > +{ > + channel &= 0x1; > + ctl &= 0x1; > + phy &= 0x1; > + writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | > + CRU_SFTRST_DDR_PHY(channel, phy), > + &cru->softrst_con[4]); > +} > + > +static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) > +{ > + rkclk_ddr_reset(cru, channel, 1, 1); > + udelay(10); > + > + rkclk_ddr_reset(cru, channel, 1, 0); > + udelay(10); > + > + rkclk_ddr_reset(cru, channel, 0, 0); > + udelay(10); > +} > + > static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, > u32 freq) > { > @@ -1129,6 +1156,7 @@ static int sdram_init(struct dram_info *dram, > { > unsigned char dramtype = params->base.dramtype; > unsigned int ddr_freq = params->base.ddr_freq; > + struct rk3399_cru *cru = dram->cru; > int channel; > int ret; > > @@ -1145,6 +1173,7 @@ static int sdram_init(struct dram_info *dram, > const struct chan_info *chan = &dram->chan[channel]; > struct rk3399_ddr_publ_regs *publ = chan->publ; > > + phy_pctrl_reset(cru, channel); > phy_dll_bypass_set(publ, ddr_freq); > > if (channel >= params->base.num_channels)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 16bd9427a6..a5da985e1a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -35,6 +35,10 @@ #define PHY_DRV_ODT_40 0xe #define PHY_DRV_ODT_34_3 0xf +#define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ + ((n) << (8 + (ch) * 4))) +#define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ + ((n) << (9 + (ch) * 4))) struct chan_info { struct rk3399_ddr_pctl_regs *pctl; struct rk3399_ddr_pi_regs *pi; @@ -79,6 +83,29 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } +static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, + u32 phy) +{ + channel &= 0x1; + ctl &= 0x1; + phy &= 0x1; + writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | + CRU_SFTRST_DDR_PHY(channel, phy), + &cru->softrst_con[4]); +} + +static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +{ + rkclk_ddr_reset(cru, channel, 1, 1); + udelay(10); + + rkclk_ddr_reset(cru, channel, 1, 0); + udelay(10); + + rkclk_ddr_reset(cru, channel, 0, 0); + udelay(10); +} + static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq) { @@ -1129,6 +1156,7 @@ static int sdram_init(struct dram_info *dram, { unsigned char dramtype = params->base.dramtype; unsigned int ddr_freq = params->base.ddr_freq; + struct rk3399_cru *cru = dram->cru; int channel; int ret; @@ -1145,6 +1173,7 @@ static int sdram_init(struct dram_info *dram, const struct chan_info *chan = &dram->chan[channel]; struct rk3399_ddr_publ_regs *publ = chan->publ; + phy_pctrl_reset(cru, channel); phy_dll_bypass_set(publ, ddr_freq); if (channel >= params->base.num_channels)