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[209.85.220.65]) by mx.google.com with SMTPS id t21sor24992528pjw.19.2019.07.16.04.58.11 for (Google Transport Security); Tue, 16 Jul 2019 04:58:11 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:8d09:: with SMTP id c9mr36387626pjo.131.1563278290740; Tue, 16 Jul 2019 04:58:10 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id z24sm36269566pfr.51.2019.07.16.04.58.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jul 2019 04:58:10 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: Manivannan Sadhasivam , gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 04/57] ram: rk3399: Add chipinfo macro Date: Tue, 16 Jul 2019 17:26:52 +0530 Message-Id: <20190716115745.12585-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190716115745.12585-1-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=dCY0FXfs; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add simplified and meaningful macro for chip info. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 + drivers/ram/rockchip/sdram_rk3399.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index e5af3eab7e..2d0be920d9 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -73,6 +73,7 @@ struct sdram_base_params { #define SYS_REG_ROW_3_4_MASK 1 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_ENC_CHINFO(ch) (1 << SYS_REG_CHINFO_SHIFT(ch)) #define SYS_REG_ENC_DDRTYPE(n) ((n) << SYS_REG_DDRTYPE_SHIFT) #define SYS_REG_ENC_NUM_CH(n) (((n) - SYS_REG_NUM_CH_MASK) << \ SYS_REG_NUM_CH_SHIFT) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index d97efb6996..874e896369 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1090,7 +1090,7 @@ static void dram_all_config(struct dram_info *dram, continue; idx++; sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel); - sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); + sys_reg |= SYS_REG_ENC_CHINFO(channel); sys_reg |= (info->cap_info.rank - 1) << SYS_REG_RANK_SHIFT(channel); sys_reg |= (info->cap_info.col - 9) <<