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[209.85.220.65]) by mx.google.com with SMTPS id c9sor3495699pgn.74.2019.07.16.04.58.29 for (Google Transport Security); Tue, 16 Jul 2019 04:58:29 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a65:500a:: with SMTP id f10mr2092494pgo.105.1563278308911; Tue, 16 Jul 2019 04:58:28 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id z24sm36269566pfr.51.2019.07.16.04.58.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jul 2019 04:58:28 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: Manivannan Sadhasivam , gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 09/57] ram: rk3399: Add cs0_rw macro Date: Tue, 16 Jul 2019 17:26:57 +0530 Message-Id: <20190716115745.12585-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190716115745.12585-1-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=PcmLxSbV; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add simplified and meaningful macro for cs0_rw. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++ drivers/ram/rockchip/sdram_rk3399.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 338f4043e1..ad9726a57c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -90,6 +90,8 @@ struct sdram_base_params { SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ + SYS_REG_CS0_ROW_SHIFT(ch)) #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index b994134fdb..43cf597828 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1094,8 +1094,7 @@ static void dram_all_config(struct dram_info *dram, sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel); sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel); - sys_reg |= (info->cap_info.cs0_row - 13) << - SYS_REG_CS0_ROW_SHIFT(channel); + sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); sys_reg |= (info->cap_info.cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); sys_reg |= (2 >> info->cap_info.bw) <<