| Message ID | 20190716115745.12585-14-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On 2019/7/16 下午7:57, Jagan Teki wrote: > cs0_row can handle the pmu via sys_reg2 and sys_reg3 while > configuring the dram instead of just sys_reg2. > > So, update cs0_row macro to make use of both sys_reg2, > sys_reg3. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com> Thanks, - Kever > --- > arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++-- > drivers/ram/rockchip/sdram_rk3399.c | 4 +++- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h > index 4749233226..f74377225c 100644 > --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h > +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h > @@ -90,8 +90,6 @@ struct sdram_base_params { > SYS_REG_BK_SHIFT(ch)) > #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) > #define SYS_REG_CS0_ROW_MASK 3 > -#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ > - SYS_REG_CS0_ROW_SHIFT(ch)) > #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) > #define SYS_REG_CS1_ROW_MASK 3 > #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ > @@ -103,6 +101,12 @@ struct sdram_base_params { > #define SYS_REG_DBW_MASK 3 > #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) > > +#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ > + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ > + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ > + (5 + 2 * (ch)); \ > + } while (0) > + > /* Get sdram size decode from reg */ > size_t rockchip_sdram_size(phys_addr_t reg); > > diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c > index 2ef969c07b..70867cbd5f 100644 > --- a/drivers/ram/rockchip/sdram_rk3399.c > +++ b/drivers/ram/rockchip/sdram_rk3399.c > @@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram, > const struct rk3399_sdram_params *params) > { > u32 sys_reg2 = 0; > + u32 sys_reg3 = 0; > unsigned int channel, idx; > > sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); > @@ -1094,10 +1095,10 @@ static void dram_all_config(struct dram_info *dram, > sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); > sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); > sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); > - sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); > sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); > sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); > sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); > + SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); > > ddr_msch_regs = dram->chan[channel].msch; > noc_timing = ¶ms->ch[channel].noc_timings; > @@ -1119,6 +1120,7 @@ static void dram_all_config(struct dram_info *dram, > } > > writel(sys_reg2, &dram->pmugrf->os_reg2); > + writel(sys_reg3, &dram->pmugrf->os_reg3); > rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, > params->base.stride << 10); >
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 4749233226..f74377225c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -90,8 +90,6 @@ struct sdram_base_params { SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ - SYS_REG_CS0_ROW_SHIFT(ch)) #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ @@ -103,6 +101,12 @@ struct sdram_base_params { #define SYS_REG_DBW_MASK 3 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) +#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (5 + 2 * (ch)); \ + } while (0) + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 2ef969c07b..70867cbd5f 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *params) { u32 sys_reg2 = 0; + u32 sys_reg3 = 0; unsigned int channel, idx; sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); @@ -1094,10 +1095,10 @@ static void dram_all_config(struct dram_info *dram, sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); - sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); + SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1119,6 +1120,7 @@ static void dram_all_config(struct dram_info *dram, } writel(sys_reg2, &dram->pmugrf->os_reg2); + writel(sys_reg3, &dram->pmugrf->os_reg3); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, params->base.stride << 10);