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[209.85.220.65]) by mx.google.com with SMTPS id h3sor24648658pld.23.2019.07.16.04.58.43 for (Google Transport Security); Tue, 16 Jul 2019 04:58:43 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:86:: with SMTP id a6mr35230478pla.244.1563278322972; Tue, 16 Jul 2019 04:58:42 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id z24sm36269566pfr.51.2019.07.16.04.58.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jul 2019 04:58:42 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: Manivannan Sadhasivam , gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 13/57] ram: rk3399: Update cs0_row to use sys_reg3 Date: Tue, 16 Jul 2019 17:27:01 +0530 Message-Id: <20190716115745.12585-14-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190716115745.12585-1-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=MEbkTo6D; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , cs0_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2. So, update cs0_row macro to make use of both sys_reg2, sys_reg3. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++-- drivers/ram/rockchip/sdram_rk3399.c | 4 +++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h index 4749233226..f74377225c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_common.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -90,8 +90,6 @@ struct sdram_base_params { SYS_REG_BK_SHIFT(ch)) #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) #define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << \ - SYS_REG_CS0_ROW_SHIFT(ch)) #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) #define SYS_REG_CS1_ROW_MASK 3 #define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << \ @@ -103,6 +101,12 @@ struct sdram_base_params { #define SYS_REG_DBW_MASK 3 #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch)) +#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \ + (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \ + (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \ + (5 + 2 * (ch)); \ + } while (0) + /* Get sdram size decode from reg */ size_t rockchip_sdram_size(phys_addr_t reg); diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 2ef969c07b..70867cbd5f 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram, const struct rk3399_sdram_params *params) { u32 sys_reg2 = 0; + u32 sys_reg3 = 0; unsigned int channel, idx; sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype); @@ -1094,10 +1095,10 @@ static void dram_all_config(struct dram_info *dram, sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel); sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel); sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel); - sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel); sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel); sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel); sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel); + SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel); ddr_msch_regs = dram->chan[channel].msch; noc_timing = ¶ms->ch[channel].noc_timings; @@ -1119,6 +1120,7 @@ static void dram_all_config(struct dram_info *dram, } writel(sys_reg2, &dram->pmugrf->os_reg2); + writel(sys_reg3, &dram->pmugrf->os_reg3); rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, params->base.stride << 10);