From patchwork Tue Jul 16 11:57:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 784 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id E80953F08F for ; Tue, 16 Jul 2019 14:00:02 +0200 (CEST) Received: by mail-pl1-f200.google.com with SMTP id 65sf10057615plf.16 for ; Tue, 16 Jul 2019 05:00:02 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1563278401; cv=pass; d=google.com; s=arc-20160816; b=x4/O50NOH7Fn1QtzTCrkv/4h38wSBAW2dexht8YDURcohnUCezcjbFTtJSjBn7+EQS feKowhmncG4CyOI90JRFZNrKYBt+LL2n3g4zc7TmVWfT0FutLtg/CdxGmUjql9Q6gOgj K3Ff40Nc6PF8ZQFdgUmDTAUIcbV4ZB8LrgmKLODXDlqm2c02zlQP7/0QcYqDGxkV+O1A zonRgoG6IHF1jzPaUZ3/sB80/UbMHceS0odr+fLqVO1eoMd1QxWqQ9mEypJKy131ysV/ Y76kJ+vQx4PUnwmdSqIO1oEIfMXMJ00+luzdbJfCb6BVt4Uq8IY8hNMTIiOWj2t5dg1j lp2w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=DmrROdBtvJjFEYt8dl+7/aW7ZmdwWLww13i1/3N2mh8=; b=jgziWeP8OcouKlLoxsoPf+ittKpvQR3ffpAa0EKfdKHODFzWzpPVEIwOnZGPHtO6PF 6fpri7b01zwfMbu/VctmDM3uQew5iBBlgIUFZnXAYlfju9sXV1kGo5krhaK0VT/m3rWN rxNYdUPgvek45WdIpyCVZ2dG7aq+EMJbQLkO14a4PL+xmG14twYfZg7siBa+6tWI4Nh6 y6dMh3CbMFEoLLIEzR01gHMaPMaBFw+EjVglX54O6hFalJjLR2dF1OS1Qz0Bj5EBbqgT wFbzRP10RQMbuP0N6ShAD4plHldpmJgdYBnWbK5xduPZXVTQnQYhMt8do7ZCT91gVP9Z 7Vtg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GKyNTgUx; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=DmrROdBtvJjFEYt8dl+7/aW7ZmdwWLww13i1/3N2mh8=; b=czIKVaE5EAzF652gH7kuocgKCD1lOmx/NSVPIQFYAbI8DJQoGNkI23WV/DB4c36B7J Aq0kBGyPJ2QYCdtk6OKhdv/qAZgF5ZkO+Lp9ahIU4vYiZmJd+PSGFlc0QAUqxRHu+f1S +9cCYN/b4A79iVzEq7Vb7OsIKgbddkoWHSad8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-spam-checked-in-group:list-post:list-help:list-archive :list-unsubscribe; bh=DmrROdBtvJjFEYt8dl+7/aW7ZmdwWLww13i1/3N2mh8=; b=SezkOrQrV9YrT2YC2OADJBk/HO5ACETRyHSDabD3AH/QodE6fYnbAe2qwq3mVKnvpS N7ehHsmxTbkYlNmbzJEizhx/gCgiZfJiqf9CTJN7JNnz+xgdbD6l7qYGrRJfZ9KKpuPi FiqDYtcg1mAGfIL1kzRG4tBpGFoSHwXhNs6mTnkOunyLaVr8VMmX0/DVy5flGDsb7c4A yFSbhuT+QrszvMjBUpM2FR4StZQdnWLOCn4WGWzzv04lDHeh5R4drIr9aMsiOT6vUYxu lWoOUJoKzK+VQrLYMUvXQ4jFtb0iDC5RJnCElBzU5iMlhSFPm09//fUl93PY6Q/zyOZ9 M0RA== X-Gm-Message-State: APjAAAVksq4JC5uk28Bw/VCF9t+Em9QyXxU+MWQAB4B/nKjqJxmJXPTa tkgMZD5kTUcEVE1OWnA1+cqNjX/X X-Google-Smtp-Source: APXvYqzcHJ+0QNzgbJIjEoOW0Pr9iVLOKvesKddDN+nGtO/K2PfSg1030xJiWQ/DdaqYrFlmSRH7Yw== X-Received: by 2002:a17:902:2006:: with SMTP id n6mr35563978pla.232.1563278401736; Tue, 16 Jul 2019 05:00:01 -0700 (PDT) X-BeenThere: linux-amarula@amarulasolutions.com Received: by 2002:a17:902:b48c:: with SMTP id y12ls5465328plr.4.gmail; Tue, 16 Jul 2019 05:00:01 -0700 (PDT) X-Received: by 2002:a17:90a:8a84:: with SMTP id x4mr35087827pjn.105.1563278401440; Tue, 16 Jul 2019 05:00:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563278401; cv=none; d=google.com; s=arc-20160816; b=Bp0nVTSVRqhm86m+bYY2bHlUttp1ZevK4pTBWsAJ1IFULYe7n+2NsallnrppTtFj5D YaVtQDmlMDtFsT2cGnRiKMNLJgzFyEhzWDKPkVDDxvLo6Vk7ijrOFYr3XwPJFH3Pq1rb W6HgBDCX3MNoViH6Qk8N/djp1Dqi0puT7gPPOJP8NjiNLwsmGLXSpK7dr+QjgJiJK9s2 2drLXFjKcJob868H71dmSdBo0tzXuQINNtVeNTtvAF+pk7mYjqOOGU60gEdPzzUSpLs7 IeFKwXQIeJ+P/tFYaFtGfIKxW6OeNFBrzTlQOR3QLu6nJDm/G4Vy2IfiylQOjpbrW6SH +78A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TGL2vZAdQiuNUHRO4mTXKyX2zgq3XTrcqwdNqg+WCgA=; b=FbdQI8CcR7jsiHoGAno4wNzvLE8B5GiMNU8Y/wtgM8qJxcJBcC1++7ib8Ei899UInI HQRzY/B4brRHDSBgMIwZyPDtZQYDCgelHj+zSTYG97WN+5aQbYWOMNlZL+j0Pe03gFwE 6xnwuDTrzoKA1EGNaWD2QpFEvgW+wClyC+jdmX4rz7FUbH+pN/EKQQgwNoeWr5NZ4FRt Zu9b5cPr1o8/NVL+K/HeUg+kQCJRrRBWMkWLIypzbqEg0+WOHEAQPDJzZIKAdpIbxram nVoCCjBq5cuaH32Oc3t97MQAn8LmB3f45ew0KlULSnhMWJe+U6fE3esbWwPcI8oa4Wsl USTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GKyNTgUx; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Received: from mail-sor-f65.google.com (mail-sor-f65.google.com. [209.85.220.65]) by mx.google.com with SMTPS id p1sor25513716pjr.9.2019.07.16.05.00.01 for (Google Transport Security); Tue, 16 Jul 2019 05:00:01 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:90a:30e4:: with SMTP id h91mr34311060pjb.37.1563278401129; Tue, 16 Jul 2019 05:00:01 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id z24sm36269566pfr.51.2019.07.16.04.59.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jul 2019 05:00:00 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Cc: Manivannan Sadhasivam , gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki Subject: [PATCH v3 35/57] ram: rk3399: Add tsel control clock drive Date: Tue, 16 Jul 2019 17:27:23 +0530 Message-Id: <20190716115745.12585-36-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190716115745.12585-1-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=GKyNTgUx; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings. Add support for these control clock for all dramtype sdrams. Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables. tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 1b8ce5160f..c38ea1d284 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_idle_select_n, tsel_rd_select_n; u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p; u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; + u32 tsel_ckcs_select_p, tsel_ckcs_select_n; struct io_setting *io = NULL; u32 reg_value; @@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = io->wr_ca_drv; tsel_wr_select_ca_n = PHY_DRV_ODT_40; + + tsel_ckcs_select_p = io->wr_ckcs_drv; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_48; tsel_wr_select_ca_n = PHY_DRV_ODT_48; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } else { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_240; @@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_select_ca_p = PHY_DRV_ODT_34_3; tsel_wr_select_ca_n = PHY_DRV_ODT_34_3; + + tsel_ckcs_select_p = PHY_DRV_ODT_34_3; + tsel_ckcs_select_n = PHY_DRV_ODT_34_3; } if (params->base.odt == 1) @@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan, clrsetbits_le32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits_le32(&denali_phy[939], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits_le32(&denali_phy[929], 0xff, + tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4)); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ clrsetbits_le32(&denali_phy[924], 0xff,