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[209.85.220.65]) by mx.google.com with SMTPS id w18sor22996350plp.50.2019.10.22.10.55.40 for (Google Transport Security); Tue, 22 Oct 2019 10:55:40 -0700 (PDT) Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; X-Received: by 2002:a17:902:fe8c:: with SMTP id x12mr5207965plm.55.1571766940354; Tue, 22 Oct 2019 10:55:40 -0700 (PDT) Received: from localhost.localdomain ([115.97.180.31]) by smtp.gmail.com with ESMTPSA id b3sm20454775pfd.125.2019.10.22.10.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2019 10:55:39 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich Cc: Levin Du , u-boot@lists.denx.de, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki , Marek Vasut Subject: [PATCH 6/9] usb: dwc3: Add phy interface for dwc3_uboot Date: Tue, 22 Oct 2019 23:24:55 +0530 Message-Id: <20191022175458.22604-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20191022175458.22604-1-jagan@amarulasolutions.com> References: <20191022175458.22604-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: jagan@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=muO1CP3w; spf=pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jagan@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , U-Boot has two different variants of dwc3 initializations, - with dm variant gadget, so the respective dm driver would call the dwc3_init in core. - with non-dm variant gadget, so the usage board file would call dwc3_uboot_init in core. The driver probe would handle all respective gadget properties including phy interface via phy_type property and then trigger dwc3_init for dm-variant gadgets. So, to support the phy interface for non-dm variant gadgets, the better option is dwc3_uboot_init since there is no dedicated controller for non-dm variant gadgets. This patch support for adding phy interface like 8/16-bit UTMI+ code for dwc3_uboot. This change used Linux phy.h enum list, to make proper code compatibility. Cc: Marek Vasut Signed-off-by: Jagan Teki --- drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 12 ++++++++++++ include/dwc3-uboot.h | 2 ++ include/linux/usb/phy.h | 19 +++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 include/linux/usb/phy.h diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 2498f0efb1..3e2295d75c 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -600,6 +600,30 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) } } +static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev, struct dwc3 *dwc) +{ + enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode; + u32 reg; + + /* Set dwc3 usb2 phy config */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg |= DWC3_GUSB2PHYCFG_PHYIF; + reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; + + switch (hsphy_mode) { + case USBPHY_INTERFACE_MODE_UTMI: + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; + break; + case USBPHY_INTERFACE_MODE_UTMIW: + reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; + break; + default: + break; + } + + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); +} + #define DWC3_ALIGN_MASK (16 - 1) /** @@ -708,6 +732,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) goto err0; } + dwc3_uboot_hsphy_mode(dwc3_dev, dwc); + ret = dwc3_event_buffers_setup(dwc); if (ret) { dev_err(dwc->dev, "failed to setup event buffers\n"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index cfe29884e7..c6888064b4 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -162,6 +162,18 @@ /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3) + +/* Global USB2 PHY Configuration Mask */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10) + +/* Global USB2 PHY Configuration Offset */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10 + +#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \ + DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET) /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index 9941cc37a3..3c9e204cf0 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -10,10 +10,12 @@ #define __DWC3_UBOOT_H_ #include +#include struct dwc3_device { unsigned long base; enum usb_dr_mode dr_mode; + enum usb_phy_interface hsphy_mode; u32 maximum_speed; unsigned tx_fifo_resize:1; unsigned has_lpm_erratum; diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h new file mode 100644 index 0000000000..158ca9cd85 --- /dev/null +++ b/include/linux/usb/phy.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * USB PHY defines + * + * These APIs may be used between USB controllers. USB device drivers + * (for either host or peripheral roles) don't use these calls; they + * continue to use just usb_device and usb_gadget. + */ + +#ifndef __LINUX_USB_PHY_H +#define __LINUX_USB_PHY_H + +enum usb_phy_interface { + USBPHY_INTERFACE_MODE_UNKNOWN, + USBPHY_INTERFACE_MODE_UTMI, + USBPHY_INTERFACE_MODE_UTMIW, +}; + +#endif /* __LINUX_USB_PHY_H */