| Message ID | 20181210161729.29720-18-jagan@amarulasolutions.com |
|---|---|
| State | New |
| Headers | show |
| Series |
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| Related | show |
On Mon, Dec 10, 2018 at 09:47:29PM +0530, Jagan Teki wrote: > The A64 has a MIPI-DSI block which is similar to A31 > without mod clock. > > So, add dsi node with A64 compatible, dphy node with > A31 compatible and finally connect dsi to tcon0 to > make proper DSI pipeline. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > index dd5740bc3fc9..dd5c7ad55149 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -344,6 +344,12 @@ > #address-cells = <1>; > #size-cells = <0>; > reg = <1>; > + > + tcon0_out_dsi: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&dsi_in_tcon0>; > + allwinner,tcon-channel = <1>; > + }; > }; > }; > }; > @@ -910,6 +916,45 @@ > status = "disabled"; > }; > > + dsi: dsi@1ca0000 { > + compatible = "allwinner,sun50i-a64-mipi-dsi"; > + reg = <0x01ca0000 0x1000>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MIPI_DSI>; > + clock-names = "bus"; > + resets = <&ccu RST_BUS_MIPI_DSI>; > + phys = <&dphy>; > + phy-names = "dphy"; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + > + dsi_in_tcon0: endpoint { > + remote-endpoint = <&tcon0_out_dsi>; > + }; The reg address-cells and size-cells properties will generate DTC warnings when compiled with W=1, please fix them. Maxime
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index dd5740bc3fc9..dd5c7ad55149 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -344,6 +344,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; }; }; }; @@ -910,6 +916,45 @@ status = "disabled"; }; + dsi: dsi@1ca0000 { + compatible = "allwinner,sun50i-a64-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MIPI_DSI>; + clock-names = "bus"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; + }; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun50i-a64-mipi-dphy", + "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + csi: csi@1cb0000 { compatible = "allwinner,sun50i-a64-csi"; reg = <0x01cb0000 0x1000>;
The A64 has a MIPI-DSI block which is similar to A31 without mod clock. So, add dsi node with A64 compatible, dphy node with A31 compatible and finally connect dsi to tcon0 to make proper DSI pipeline. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+)