diff mbox series

[v3,09/15] ram: rk3399: Order tsel variables

Message ID	20190715182110.21336-10-jagan@amarulasolutions.com
State	New
Headers	Received-SPF: pass (google.com: domain of jagan@amarulasolutions.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; From: Jagan Teki <jagan@amarulasolutions.com> To: Simon Glass <sjg@chromium.org>, Philipp Tomsich <philipp.tomsich@theobroma-systems.com>, Kever Yang <kever.yang@rock-chips.com>, YouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, gajjar04akash@gmail.com, linux-rockchip@lists.infradead.org, linux-amarula@amarulasolutions.com, Jagan Teki <jagan@amarulasolutions.com> Subject: [PATCH v3 09/15] ram: rk3399: Order tsel variables Date: Mon, 15 Jul 2019 23:51:04 +0530 Message-Id: <20190715182110.21336-10-jagan@amarulasolutions.com> In-Reply-To: <20190715182110.21336-1-jagan@amarulasolutions.com> References: <20190715182110.21336-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com
Series	ram: rk3399: Code cleanup \| [v3,00/15] ram: rk3399: Code cleanup [v3,01/15] ram: rk3399: Fix code warnings [v3,02/15] ram: rk3399: Some trivial code fixes [v3,03/15] ram: rk3399: s/sdram_params/params [v3,04/15] ram: rk3399: Handle pctl_cfg return type [v3,05/15] ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n [v3,06/15] ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_p [v3,07/15] ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_n [v3,08/15] ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_p [v3,09/15] ram: rk3399: Order tsel variables [v3,10/15] ram: rockchip: rk3399: Add cap_info structure [v3,11/15] ram: rk3399: s/rk3399_base_params/sdram_base_params [v3,12/15] ram: rk3399: Move common sdram structures in common header [v3,13/15] arm: include: rockchip: Move dramtypes to common header [v3,14/15] arm: include: rockchip: Add DDR4 enum [v3,15/15] clk: rockchip: rk3399: Fix check patch warnings and checks

Commit Message

Jagan Teki July 15, 2019, 6:21 p.m. UTC

Order tsel* variable declarations and assignment in proper
and meaningful way.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
 1 file changed, 22 insertions(+), 15 deletions(-)

Comments

Kever Yang July 16, 2019, 7:32 a.m. UTC | #1

On 2019/7/16 上午2:21, Jagan Teki wrote:
> Order tsel* variable declarations and assignment in proper
> and meaningful way.
>
> No functionality change.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
>   1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 8a983f9bb1..043b27737d 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -159,41 +159,48 @@ static void set_ds_odt(const struct chan_info *chan,
>   	u32 *denali_phy = chan->publ->denali_phy;
>   
>   	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
> -	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
> -	u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
> -	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
> +	u32 tsel_idle_select_p, tsel_rd_select_p;
> +	u32 tsel_idle_select_n, tsel_rd_select_n;
> +	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
> +	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
>   	u32 reg_value;
>   
>   	if (params->base.dramtype == LPDDR4) {
>   		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
> -		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
> -		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
> +		tsel_rd_select_n = PHY_DRV_ODT_240;
> +
>   		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
> +		tsel_idle_select_n = PHY_DRV_ODT_240;
>   
> -		tsel_rd_select_n = PHY_DRV_ODT_240;
> +		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
>   		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
> +
> +		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
>   		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
> -		tsel_idle_select_n = PHY_DRV_ODT_240;
>   	} else if (params->base.dramtype == LPDDR3) {
>   		tsel_rd_select_p = PHY_DRV_ODT_240;
> -		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
> -		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
> +		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
> +
>   		tsel_idle_select_p = PHY_DRV_ODT_240;
> +		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
>   
> -		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
> +		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
>   		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
> +
> +		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
>   		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
> -		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
>   	} else {
>   		tsel_rd_select_p = PHY_DRV_ODT_240;
> -		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
> -		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
> +		tsel_rd_select_n = PHY_DRV_ODT_240;
> +
>   		tsel_idle_select_p = PHY_DRV_ODT_240;
> +		tsel_idle_select_n = PHY_DRV_ODT_240;
>   
> -		tsel_rd_select_n = PHY_DRV_ODT_240;
> +		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
>   		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
> +
> +		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
>   		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
> -		tsel_idle_select_n = PHY_DRV_ODT_240;
>   	}
>   
>   	if (params->base.odt == 1)

diff mbox series

Patch

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 8a983f9bb1..043b27737d 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -159,41 +159,48 @@  static void set_ds_odt(const struct chan_info *chan,
 	u32 *denali_phy = chan->publ->denali_phy;
 
 	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
-	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
-	u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
-	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
+	u32 tsel_idle_select_p, tsel_rd_select_p;
+	u32 tsel_idle_select_n, tsel_rd_select_n;
+	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
+	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 	u32 reg_value;
 
 	if (params->base.dramtype == LPDDR4) {
 		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+		tsel_rd_select_n = PHY_DRV_ODT_240;
+
 		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
+		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
-		tsel_idle_select_n = PHY_DRV_ODT_240;
 	} else if (params->base.dramtype == LPDDR3) {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
+		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+
 		tsel_idle_select_p = PHY_DRV_ODT_240;
+		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 
-		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
-		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 	} else {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
+		tsel_rd_select_n = PHY_DRV_ODT_240;
+
 		tsel_idle_select_p = PHY_DRV_ODT_240;
+		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
-		tsel_idle_select_n = PHY_DRV_ODT_240;
 	}
 
 	if (params->base.odt == 1)