diff mbox series

[v3,18/57] ram: rk3399: Add DdrMode

Message ID 20190716115745.12585-19-jagan@amarulasolutions.com
State New
Headers
Series ram: rk3399: Add LPDDR4 support |

Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC 
Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 .../include/asm/arch-rockchip/sdram_rk3399.h    | 17 ++++++++++++++++-
 drivers/ram/rockchip/sdram_rk3399.c             |  2 +-
 2 files changed, 17 insertions(+), 2 deletions(-)

Comments

Kever Yang July 16, 2019, 1:02 p.m. UTC | #1 
On 2019/7/16 下午7:57, Jagan Teki wrote:
> Add DdrMode structure with associated bit fields.
>
> These would help to reconfigure sdram capabilities during
> lpddr4 setup related configs.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   .../include/asm/arch-rockchip/sdram_rk3399.h    | 17 ++++++++++++++++-
>   drivers/ram/rockchip/sdram_rk3399.c             |  2 +-
>   2 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
> index 7f41a67242..dc65ae7924 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
> @@ -28,6 +28,21 @@ union noc_ddrtimingc0 {
>   	} b;
>   };
>   
> +union noc_ddrmode {
> +	u32 d32;
> +	struct {
> +		unsigned autoprecharge : 1;
> +		unsigned bypassfiltering : 1;
> +		unsigned fawbank : 1;
> +		unsigned burstsize : 2;
> +		unsigned mwrsize : 2;
> +		unsigned reserved2 : 1;
> +		unsigned forceorder : 8;
> +		unsigned forceorderstate : 8;
> +		unsigned reserved3 : 8;
> +	} b;
> +};
> +
>   struct rk3399_msch_regs {
>   	u32 coreid;
>   	u32 revisionid;
> @@ -48,7 +63,7 @@ struct rk3399_msch_timings {
>   	u32 ddrtimingb0;
>   	union noc_ddrtimingc0 ddrtimingc0;
>   	u32 devtodev0;
> -	u32 ddrmode;
> +	union noc_ddrmode ddrmode;
>   	u32 agingx0;
>   };
>   
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index e916448fc0..e4723c7d59 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -1114,7 +1114,7 @@ static void dram_all_config(struct dram_info *dram,
>   		       &ddr_msch_regs->ddrtimingc0);
>   		writel(noc_timing->devtodev0,
>   		       &ddr_msch_regs->devtodev0);
> -		writel(noc_timing->ddrmode,
> +		writel(noc_timing->ddrmode.d32,
>   		       &ddr_msch_regs->ddrmode);
>   
>   		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
index 7f41a67242..dc65ae7924 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h
@@ -28,6 +28,21 @@  union noc_ddrtimingc0 {
 	} b;
 };
 
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge : 1;
+		unsigned bypassfiltering : 1;
+		unsigned fawbank : 1;
+		unsigned burstsize : 2;
+		unsigned mwrsize : 2;
+		unsigned reserved2 : 1;
+		unsigned forceorder : 8;
+		unsigned forceorderstate : 8;
+		unsigned reserved3 : 8;
+	} b;
+};
+
 struct rk3399_msch_regs {
 	u32 coreid;
 	u32 revisionid;
@@ -48,7 +63,7 @@  struct rk3399_msch_timings {
 	u32 ddrtimingb0;
 	union noc_ddrtimingc0 ddrtimingc0;
 	u32 devtodev0;
-	u32 ddrmode;
+	union noc_ddrmode ddrmode;
 	u32 agingx0;
 };
 
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index e916448fc0..e4723c7d59 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1114,7 +1114,7 @@  static void dram_all_config(struct dram_info *dram,
 		       &ddr_msch_regs->ddrtimingc0);
 		writel(noc_timing->devtodev0,
 		       &ddr_msch_regs->devtodev0);
-		writel(noc_timing->ddrmode,
+		writel(noc_timing->ddrmode.d32,
 		       &ddr_msch_regs->ddrmode);
 
 		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */