diff mbox series

[3/3] spi: sifive: Fix format register proto field

Message ID 20200420120921.12840-4-jagan@amarulasolutions.com
State New
Headers
Series spi: Support SPI I/O protocol lines |

Commit Message

Jagan Teki April 20, 2020, 12:09 p.m. UTC 
SiFive SPI controller has a proto bit field in frame format
register which would be used to configure the SPI I/O protocol
lines used on specific transfer. 

Right now the driver is configuring this proto using slave->mode
which is used for data transfer and opcode, address vary depending
on the particular transfer at runtime.

Now the SPI framework supports per transfer I/O protocol lines,
so use spi->proto instead of slave-mode.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/spi/spi-sifive.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

Bin Meng April 20, 2020, 11:14 p.m. UTC | #1 
On Mon, Apr 20, 2020 at 8:09 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> SiFive SPI controller has a proto bit field in frame format
> register which would be used to configure the SPI I/O protocol
> lines used on specific transfer.
>
> Right now the driver is configuring this proto using slave->mode
> which is used for data transfer and opcode, address vary depending
> on the particular transfer at runtime.
>
> Now the SPI framework supports per transfer I/O protocol lines,
> so use spi->proto instead of slave-mode.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/spi/spi-sifive.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>

This patch does not apply on top of u-boot/master.

Please rebase and resend.

Regards,
Bin
Sagar Kadam April 21, 2020, 3:47 p.m. UTC | #2 
Hi Bin, Jagan,

Thanks Jagan for posting the patches to enable QUAD SPI-NOR on HiFive Unleashed
along with other sequels.

> -----Original Message-----
> From: Bin Meng <bmeng.cn@gmail.com>
> Sent: Tuesday, April 21, 2020 4:44 AM
> To: Jagan Teki <jagan@amarulasolutions.com>
> Cc: Vignesh R <vigneshr@ti.com>; U-Boot Mailing List <u-
> boot@lists.denx.de>; Suneel Garapati <suneelglinux@gmail.com>; Sagar
> Kadam <sagar.kadam@sifive.com>; Bhargav Shah
> <bhargavshah1988@gmail.com>; Simon Glass <sjg@chromium.org>; Tom
> Rini <trini@konsulko.com>; linux-amarula <linux-
> amarula@amarulasolutions.com>
> Subject: Re: [PATCH 3/3] spi: sifive: Fix format register proto field
> 
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
> 
> On Mon, Apr 20, 2020 at 8:09 PM Jagan Teki
> <jagan@amarulasolutions.com> wrote:
> >
> > SiFive SPI controller has a proto bit field in frame format register
> > which would be used to configure the SPI I/O protocol lines used on
> > specific transfer.
> >
> > Right now the driver is configuring this proto using slave->mode which
> > is used for data transfer and opcode, address vary depending on the
> > particular transfer at runtime.
> >
> > Now the SPI framework supports per transfer I/O protocol lines, so use
> > spi->proto instead of slave-mode.
> >
> > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > ---
> >  drivers/spi/spi-sifive.c | 11 ++++++++---
> >  1 file changed, 8 insertions(+), 3 deletions(-)
> >
> 

> This patch does not apply on top of u-boot/master.
> 
> Please rebase and resend.

I guess Bin, you will also have to add following two patch series [1] and [2] before this set.
I tested this and other series with following dependency chain over 
u-boot/master(e4837da7828293ea49abc579f939c0f5c4b127c3)

1> 1-2-mtd-spi-nor-Enable-QE-bit-for-ISSI-flash.patch
2> spi-sifive-Tidy-up-dm_spi_slave_platdata-variable.patch
3> spi: Support SPI I/O protocol lines
4> riscv: sifive/fu540: Enable SPI-NOR support

I could verify flash erase/read/write operations along with mmc spi.

[1] https://patchwork.ozlabs.org/project/uboot/patch/20200420100607.23009-1-jagan@amarulasolutions.com/
[2] https://patchwork.amarulasolutions.com/patch/1083/


Thanks & BR,
Sagar Kadam

> 
> Regards,
> Bin
Jagan Teki April 23, 2020, 5:05 p.m. UTC | #3 
Hi Sagar and Bin,

On Tue, Apr 21, 2020 at 9:17 PM Sagar Kadam <sagar.kadam@sifive.com> wrote:
>
> Hi Bin, Jagan,
>
> Thanks Jagan for posting the patches to enable QUAD SPI-NOR on HiFive Unleashed
> along with other sequels.
>
> > -----Original Message-----
> > From: Bin Meng <bmeng.cn@gmail.com>
> > Sent: Tuesday, April 21, 2020 4:44 AM
> > To: Jagan Teki <jagan@amarulasolutions.com>
> > Cc: Vignesh R <vigneshr@ti.com>; U-Boot Mailing List <u-
> > boot@lists.denx.de>; Suneel Garapati <suneelglinux@gmail.com>; Sagar
> > Kadam <sagar.kadam@sifive.com>; Bhargav Shah
> > <bhargavshah1988@gmail.com>; Simon Glass <sjg@chromium.org>; Tom
> > Rini <trini@konsulko.com>; linux-amarula <linux-
> > amarula@amarulasolutions.com>
> > Subject: Re: [PATCH 3/3] spi: sifive: Fix format register proto field
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > On Mon, Apr 20, 2020 at 8:09 PM Jagan Teki
> > <jagan@amarulasolutions.com> wrote:
> > >
> > > SiFive SPI controller has a proto bit field in frame format register
> > > which would be used to configure the SPI I/O protocol lines used on
> > > specific transfer.
> > >
> > > Right now the driver is configuring this proto using slave->mode which
> > > is used for data transfer and opcode, address vary depending on the
> > > particular transfer at runtime.
> > >
> > > Now the SPI framework supports per transfer I/O protocol lines, so use
> > > spi->proto instead of slave-mode.
> > >
> > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> > > ---
> > >  drivers/spi/spi-sifive.c | 11 ++++++++---
> > >  1 file changed, 8 insertions(+), 3 deletions(-)
> > >
> >
>
> > This patch does not apply on top of u-boot/master.
> >
> > Please rebase and resend.
>
> I guess Bin, you will also have to add following two patch series [1] and [2] before this set.
> I tested this and other series with following dependency chain over
> u-boot/master(e4837da7828293ea49abc579f939c0f5c4b127c3)
>
> 1> 1-2-mtd-spi-nor-Enable-QE-bit-for-ISSI-flash.patch
> 2> spi-sifive-Tidy-up-dm_spi_slave_platdata-variable.patch
> 3> spi: Support SPI I/O protocol lines
> 4> riscv: sifive/fu540: Enable SPI-NOR support
>
> I could verify flash erase/read/write operations along with mmc spi.

Send the v4 w/o any dependencies, but on top of u-boot-spi/master
tree. I/O protocol changes are now handled in spi-sifive via spi-mem
exec_op for now since the actual generic code patch[3] will take some
time to be in ML as it affects all platforms.

Please have a test at earliest.

[3] https://patchwork.ozlabs.org/project/uboot/patch/20200420120921.12840-2-jagan@amarulasolutions.com/

Jagan.
diff mbox series

Patch

diff --git a/drivers/spi/spi-sifive.c b/drivers/spi/spi-sifive.c
index 8f5efb51a3..336b683476 100644
--- a/drivers/spi/spi-sifive.c
+++ b/drivers/spi/spi-sifive.c
@@ -146,12 +146,17 @@  static void sifive_spi_prep_transfer(struct sifive_spi *spi,
 
 	/* Number of wires ? */
 	cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
-	if ((slave_plat->mode & SPI_TX_QUAD) || (slave_plat->mode & SPI_RX_QUAD))
+	switch (slave_plat->proto) {
+	case SPI_PROTO_QUAD:
 		cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
-	else if ((slave_plat->mode & SPI_TX_DUAL) || (slave_plat->mode & SPI_RX_DUAL))
+		break;
+	case SPI_PROTO_DUAL:
 		cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
-	else
+		break;
+	default:
 		cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
+		break;
+	}
 
 	/* SPI direction in/out ? */
 	cr &= ~SIFIVE_SPI_FMT_DIR;