[v3,4/4] arm: Remove netspace_v2 board
Commit Message
This board has not been converted to CONFIG_DM by the deadline.
Remove it.
Patch-cc: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v3:
- new patch
arch/arm/mach-kirkwood/Kconfig | 4 -
board/LaCie/netspace_v2/Kconfig | 12 --
board/LaCie/netspace_v2/MAINTAINERS | 14 --
board/LaCie/netspace_v2/Makefile | 10 --
board/LaCie/netspace_v2/kwbimage-is2.cfg | 149 ----------------------
board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 149 ----------------------
board/LaCie/netspace_v2/kwbimage.cfg | 149 ----------------------
board/LaCie/netspace_v2/netspace_v2.c | 120 -----------------
board/LaCie/netspace_v2/netspace_v2.h | 22 ----
configs/inetspace_v2_defconfig | 53 --------
configs/netspace_lite_v2_defconfig | 53 --------
configs/netspace_max_v2_defconfig | 53 --------
configs/netspace_mini_v2_defconfig | 48 -------
configs/netspace_v2_defconfig | 53 --------
14 files changed, 889 deletions(-)
delete mode 100644 board/LaCie/netspace_v2/Kconfig
delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS
delete mode 100644 board/LaCie/netspace_v2/Makefile
delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg
delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg
delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg
delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c
delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h
delete mode 100644 configs/inetspace_v2_defconfig
delete mode 100644 configs/netspace_lite_v2_defconfig
delete mode 100644 configs/netspace_max_v2_defconfig
delete mode 100644 configs/netspace_mini_v2_defconfig
delete mode 100644 configs/netspace_v2_defconfig
Comments
On Thu, Jun 18, 2020 at 11:15:16PM +0530, Jagan Teki wrote:
> This board has not been converted to CONFIG_DM by the deadline.
I am working at converting this board too, along with net2big_v2.
Simon
>
> Remove it.
>
> Patch-cc: Simon Guinot <simon.guinot@sequanux.org>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> Changes for v3:
> - new patch
>
> arch/arm/mach-kirkwood/Kconfig | 4 -
> board/LaCie/netspace_v2/Kconfig | 12 --
> board/LaCie/netspace_v2/MAINTAINERS | 14 --
> board/LaCie/netspace_v2/Makefile | 10 --
> board/LaCie/netspace_v2/kwbimage-is2.cfg | 149 ----------------------
> board/LaCie/netspace_v2/kwbimage-ns2l.cfg | 149 ----------------------
> board/LaCie/netspace_v2/kwbimage.cfg | 149 ----------------------
> board/LaCie/netspace_v2/netspace_v2.c | 120 -----------------
> board/LaCie/netspace_v2/netspace_v2.h | 22 ----
> configs/inetspace_v2_defconfig | 53 --------
> configs/netspace_lite_v2_defconfig | 53 --------
> configs/netspace_max_v2_defconfig | 53 --------
> configs/netspace_mini_v2_defconfig | 48 -------
> configs/netspace_v2_defconfig | 53 --------
> 14 files changed, 889 deletions(-)
> delete mode 100644 board/LaCie/netspace_v2/Kconfig
> delete mode 100644 board/LaCie/netspace_v2/MAINTAINERS
> delete mode 100644 board/LaCie/netspace_v2/Makefile
> delete mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg
> delete mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> delete mode 100644 board/LaCie/netspace_v2/kwbimage.cfg
> delete mode 100644 board/LaCie/netspace_v2/netspace_v2.c
> delete mode 100644 board/LaCie/netspace_v2/netspace_v2.h
> delete mode 100644 configs/inetspace_v2_defconfig
> delete mode 100644 configs/netspace_lite_v2_defconfig
> delete mode 100644 configs/netspace_max_v2_defconfig
> delete mode 100644 configs/netspace_mini_v2_defconfig
> delete mode 100644 configs/netspace_v2_defconfig
>
> diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
> index ad6aef45bf..899c079773 100644
> --- a/arch/arm/mach-kirkwood/Kconfig
> +++ b/arch/arm/mach-kirkwood/Kconfig
> @@ -35,9 +35,6 @@ config TARGET_KM_KIRKWOOD
> bool "KM Kirkwood Board"
> select VENDOR_KM
>
> -config TARGET_NETSPACE_V2
> - bool "LaCie netspace_v2 Board"
> -
> config TARGET_IB62X0
> bool "ib62x0 Board"
>
> @@ -77,7 +74,6 @@ source "board/cloudengines/pogo_e02/Kconfig"
> source "board/d-link/dns325/Kconfig"
> source "board/iomega/iconnect/Kconfig"
> source "board/keymile/Kconfig"
> -source "board/LaCie/netspace_v2/Kconfig"
> source "board/raidsonic/ib62x0/Kconfig"
> source "board/Seagate/dockstar/Kconfig"
> source "board/Seagate/goflexhome/Kconfig"
> diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig
> deleted file mode 100644
> index 930b822dfb..0000000000
> --- a/board/LaCie/netspace_v2/Kconfig
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -if TARGET_NETSPACE_V2
> -
> -config SYS_BOARD
> - default "netspace_v2"
> -
> -config SYS_VENDOR
> - default "LaCie"
> -
> -config SYS_CONFIG_NAME
> - default "lacie_kw"
> -
> -endif
> diff --git a/board/LaCie/netspace_v2/MAINTAINERS b/board/LaCie/netspace_v2/MAINTAINERS
> deleted file mode 100644
> index 55fd50d4eb..0000000000
> --- a/board/LaCie/netspace_v2/MAINTAINERS
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -NETSPACE_V2 BOARD
> -M: Simon Guinot <simon.guinot@sequanux.org>
> -S: Maintained
> -F: board/LaCie/netspace_v2/
> -F: include/configs/lacie_kw.h
> -F: configs/inetspace_v2_defconfig
> -F: configs/netspace_max_v2_defconfig
> -F: configs/netspace_v2_defconfig
> -
> -NETSPACE_LITE_V2 BOARD
> -#M: -
> -S: Maintained
> -F: configs/netspace_lite_v2_defconfig
> -F: configs/netspace_mini_v2_defconfig
> diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
> deleted file mode 100644
> index a6270bdd4b..0000000000
> --- a/board/LaCie/netspace_v2/Makefile
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -
> -obj-y := netspace_v2.o ../common/common.o
> diff --git a/board/LaCie/netspace_v2/kwbimage-is2.cfg b/board/LaCie/netspace_v2/kwbimage-is2.cfg
> deleted file mode 100644
> index 50f584ae70..0000000000
> --- a/board/LaCie/netspace_v2/kwbimage-is2.cfg
> +++ /dev/null
> @@ -1,149 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x00000008 # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 10, Cs0size=512Mb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> deleted file mode 100644
> index 092353a06d..0000000000
> --- a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
> +++ /dev/null
> @@ -1,149 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000DDDD # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 10, Cs0size=512Mb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/kwbimage.cfg b/board/LaCie/netspace_v2/kwbimage.cfg
> deleted file mode 100644
> index 1ed03fa9a9..0000000000
> --- a/board/LaCie/netspace_v2/kwbimage.cfg
> +++ /dev/null
> @@ -1,149 +0,0 @@
> -# SPDX-License-Identifier: GPL-2.0+
> -#
> -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> -#
> -# Based on Kirkwood support:
> -# (C) Copyright 2009
> -# Marvell Semiconductor <www.marvell.com>
> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> -# Refer doc/README.kwbimage for more details about how-to configure
> -# and create kirkwood boot image
> -#
> -
> -# Boot Media configurations
> -BOOT_FROM spi # Boot from SPI flash
> -
> -# SOC registers configuration using bootrom header extension
> -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
> -
> -# Configure RGMII-0 interface pad voltage to 1.8V
> -DATA 0xFFD100e0 0x1B1B1B9B
> -
> -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
> -DATA 0xFFD01400 0x43000618 # DDR Configuration register
> -# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
> -# bit23-14: zero
> -# bit24: 1= enable exit self refresh mode on DDR access
> -# bit25: 1 required
> -# bit29-26: zero
> -# bit31-30: 01
> -
> -DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
> -# bit 4: 0=addr/cmd in smame cycle
> -# bit 5: 0=clk is driven during self refresh, we don't care for APX
> -# bit 6: 0=use recommended falling edge of clk for addr/cmd
> -# bit14: 0=input buffer always powered up
> -# bit18: 1=cpu lock transaction enabled
> -# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
> -# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
> -# bit30-28: 3 required
> -# bit31: 0=no additional STARTBURST delay
> -
> -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
> -# bit7-4: TRCD
> -# bit11- 8: TRP
> -# bit15-12: TWR
> -# bit19-16: TWTR
> -# bit20: TRAS msb
> -# bit23-21: 0x0
> -# bit27-24: TRRD
> -# bit31-28: TRTP
> -
> -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
> -# bit6-0: TRFC
> -# bit8-7: TR2R
> -# bit10-9: TR2W
> -# bit12-11: TW2W
> -# bit31-13: zero required
> -
> -DATA 0xFFD01410 0x0000000C # DDR Address Control
> -# bit1-0: 00, Cs0width=x8
> -# bit3-2: 11, Cs0size=1Gb
> -# bit5-4: 00, Cs2width=nonexistent
> -# bit7-6: 00, Cs1size =nonexistent
> -# bit9-8: 00, Cs2width=nonexistent
> -# bit11-10: 00, Cs2size =nonexistent
> -# bit13-12: 00, Cs3width=nonexistent
> -# bit15-14: 00, Cs3size =nonexistent
> -# bit16: 0, Cs0AddrSel
> -# bit17: 0, Cs1AddrSel
> -# bit18: 0, Cs2AddrSel
> -# bit19: 0, Cs3AddrSel
> -# bit31-20: 0 required
> -
> -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
> -# bit0: 0, OpenPage enabled
> -# bit31-1: 0 required
> -
> -DATA 0xFFD01418 0x00000000 # DDR Operation
> -# bit3-0: 0x0, DDR cmd
> -# bit31-4: 0 required
> -
> -DATA 0xFFD0141C 0x00000632 # DDR Mode
> -# bit2-0: 2, BurstLen=2 required
> -# bit3: 0, BurstType=0 required
> -# bit6-4: 4, CL=5
> -# bit7: 0, TestMode=0 normal
> -# bit8: 0, DLL reset=0 normal
> -# bit11-9: 6, auto-precharge write recovery ????????????
> -# bit12: 0, PD must be zero
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01420 0x00000004 # DDR Extended Mode
> -# bit0: 0, DDR DLL enabled
> -# bit1: 1, DDR drive strenght reduced
> -# bit2: 1, DDR ODT control lsd enabled
> -# bit5-3: 000, required
> -# bit6: 1, DDR ODT control msb, enabled
> -# bit9-7: 000, required
> -# bit10: 0, differential DQS enabled
> -# bit11: 0, required
> -# bit12: 0, DDR output buffer enabled
> -# bit31-13: 0 required
> -
> -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
> -# bit2-0: 111, required
> -# bit3 : 1 , MBUS Burst Chop disabled
> -# bit6-4: 111, required
> -# bit7 : 1 , D2P Latency enabled
> -# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
> -# bit9 : 0 , no half clock cycle addition to dataout
> -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
> -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
> -# bit15-12: 1111 required
> -# bit31-16: 0 required
> -
> -DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
> -DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
> -
> -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
> -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
> -# bit0: 1, Window enabled
> -# bit1: 0, Write Protect disabled
> -# bit3-2: 00, CS0 hit selected
> -# bit23-4: ones, required
> -# bit31-24: 0x07, Size (i.e. 128MB)
> -
> -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
> -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
> -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
> -
> -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
> -# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
> -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
> -
> -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
> -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
> -# bit3-2: 01, ODT1 active NEVER!
> -# bit31-4: zero, required
> -
> -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
> -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
> -# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
> -# bit11-10:1, DQ_ODTSel. ODT select turned on
> -
> -DATA 0xFFD01480 0x00000001 # DDR Initialization Control
> -#bit0=1, enable DDR init upon this register write
> -
> -# End of Header extension
> -DATA 0x0 0x0
> diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
> deleted file mode 100644
> index 011cc563d1..0000000000
> --- a/board/LaCie/netspace_v2/netspace_v2.c
> +++ /dev/null
> @@ -1,120 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - */
> -
> -#include <common.h>
> -#include <command.h>
> -#include <env.h>
> -#include <init.h>
> -#include <net.h>
> -#include <asm/mach-types.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/soc.h>
> -#include <asm/arch/mpp.h>
> -#include <asm/arch/gpio.h>
> -
> -#include "netspace_v2.h"
> -#include "../common/common.h"
> -
> -DECLARE_GLOBAL_DATA_PTR;
> -
> -int board_early_init_f(void)
> -{
> - /* Gpio configuration */
> - mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
> - NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
> -
> - /* Multi-Purpose Pins Functionality configuration */
> - static const u32 kwmpp_config[] = {
> - MPP0_SPI_SCn,
> - MPP1_SPI_MOSI,
> - MPP2_SPI_SCK,
> - MPP3_SPI_MISO,
> - MPP4_NF_IO6,
> - MPP5_NF_IO7,
> - MPP6_SYSRST_OUTn,
> - MPP7_GPO, /* Fan speed (bit 1) */
> - MPP8_TW_SDA,
> - MPP9_TW_SCK,
> - MPP10_UART0_TXD,
> - MPP11_UART0_RXD,
> - MPP12_GPO, /* Red led */
> - MPP14_GPIO, /* USB fuse */
> - MPP16_GPIO, /* SATA 0 power */
> - MPP17_GPIO, /* SATA 1 power */
> - MPP18_NF_IO0,
> - MPP19_NF_IO1,
> - MPP20_SATA1_ACTn,
> - MPP21_SATA0_ACTn,
> - MPP22_GPIO, /* Fan speed (bit 0) */
> - MPP23_GPIO, /* Fan power */
> - MPP24_GPIO, /* USB mode select */
> - MPP25_GPIO, /* Fan rotation fail */
> - MPP26_GPIO, /* USB vbus-in detection */
> - MPP28_GPIO, /* USB enable vbus-out */
> - MPP29_GPIO, /* Blue led (slow register) */
> - MPP30_GPIO, /* Blue led (command register) */
> - MPP31_GPIO, /* Board power off */
> - MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
> - MPP33_GPIO, /* Fan speed (bit 2) */
> - 0
> - };
> - kirkwood_mpp_conf(kwmpp_config, NULL);
> -
> - return 0;
> -}
> -
> -int board_init(void)
> -{
> - /* Machine number */
> - gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
> -
> - /* Boot parameters address */
> - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
> -
> - return 0;
> -}
> -
> -#if defined(CONFIG_MISC_INIT_R)
> -int misc_init_r(void)
> -{
> -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
> - if (!env_get("ethaddr")) {
> - uchar mac[6];
> - if (lacie_read_mac_address(mac) == 0)
> - eth_env_set_enetaddr("ethaddr", mac);
> - }
> -#endif
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
> -/* Configure and initialize PHY */
> -void reset_phy(void)
> -{
> -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
> - mv_phy_88e1318_init("egiga0", 0);
> -#else
> - mv_phy_88e1116_init("egiga0", 8);
> -#endif
> -}
> -#endif
> -
> -#if defined(CONFIG_KIRKWOOD_GPIO)
> -/* Return GPIO button status */
> -static int
> -do_read_button(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
> -{
> - return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
> -}
> -
> -U_BOOT_CMD(button, 1, 1, do_read_button,
> - "Return GPIO button status 0=off 1=on", "");
> -#endif
> diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h
> deleted file mode 100644
> index 2c930171ea..0000000000
> --- a/board/LaCie/netspace_v2/netspace_v2.h
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
> - *
> - * Based on Kirkwood support:
> - * (C) Copyright 2009
> - * Marvell Semiconductor <www.marvell.com>
> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> - */
> -
> -#ifndef NETSPACE_V2_H
> -#define NETSPACE_V2_H
> -
> -/* GPIO configuration */
> -#define NETSPACE_V2_OE_LOW 0x06004000
> -#define NETSPACE_V2_OE_HIGH 0x00000031
> -#define NETSPACE_V2_OE_VAL_LOW 0x10030000
> -#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
> -
> -#define NETSPACE_V2_GPIO_BUTTON 32
> -
> -#endif /* NETSPACE_V2_H */
> diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
> deleted file mode 100644
> index 6144eb5fad..0000000000
> --- a/configs/inetspace_v2_defconfig
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_DCACHE_OFF=y
> -CONFIG_ARCH_CPU_INIT=y
> -CONFIG_ARCH_KIRKWOOD=y
> -CONFIG_SYS_TEXT_BASE=0x600000
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x70000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_NR_DRAM_BANKS=2
> -CONFIG_IDENT_STRING=" IS v2"
> -CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
> -CONFIG_BOOTDELAY=3
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=ttyS0,115200"
> -CONFIG_USE_PREBOOT=y
> -CONFIG_CONSOLE_MUX=y
> -CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_PROMPT="ns2> "
> -CONFIG_CMD_EEPROM=y
> -CONFIG_CMD_IDE=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_ISO_PARTITION=y
> -CONFIG_EFI_PARTITION=y
> -# CONFIG_PARTITION_UUIDS is not set
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2"
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_USE_ENV_SPI_MAX_HZ=y
> -CONFIG_ENV_SPI_MAX_HZ=20000000
> -CONFIG_ENV_ADDR=0x70000
> -CONFIG_MVSATA_IDE=y
> -# CONFIG_MMC is not set
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_MACRONIX=y
> -CONFIG_MVGBE=y
> -CONFIG_MII=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_KIRKWOOD_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_STORAGE=y
> diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
> deleted file mode 100644
> index c744d2c58e..0000000000
> --- a/configs/netspace_lite_v2_defconfig
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_DCACHE_OFF=y
> -CONFIG_ARCH_CPU_INIT=y
> -CONFIG_ARCH_KIRKWOOD=y
> -CONFIG_SYS_TEXT_BASE=0x600000
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x70000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_NR_DRAM_BANKS=2
> -CONFIG_IDENT_STRING=" NS v2 Lite"
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
> -CONFIG_BOOTDELAY=3
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=ttyS0,115200"
> -CONFIG_USE_PREBOOT=y
> -CONFIG_CONSOLE_MUX=y
> -CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_PROMPT="ns2> "
> -CONFIG_CMD_EEPROM=y
> -CONFIG_CMD_IDE=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_ISO_PARTITION=y
> -CONFIG_EFI_PARTITION=y
> -# CONFIG_PARTITION_UUIDS is not set
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite"
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_USE_ENV_SPI_MAX_HZ=y
> -CONFIG_ENV_SPI_MAX_HZ=20000000
> -CONFIG_ENV_ADDR=0x70000
> -CONFIG_MVSATA_IDE=y
> -# CONFIG_MMC is not set
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_MACRONIX=y
> -CONFIG_MVGBE=y
> -CONFIG_MII=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_KIRKWOOD_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_STORAGE=y
> diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
> deleted file mode 100644
> index 8602729fcb..0000000000
> --- a/configs/netspace_max_v2_defconfig
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_DCACHE_OFF=y
> -CONFIG_ARCH_CPU_INIT=y
> -CONFIG_ARCH_KIRKWOOD=y
> -CONFIG_SYS_TEXT_BASE=0x600000
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x70000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_NR_DRAM_BANKS=2
> -CONFIG_IDENT_STRING=" NS Max v2"
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
> -CONFIG_BOOTDELAY=3
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=ttyS0,115200"
> -CONFIG_USE_PREBOOT=y
> -CONFIG_CONSOLE_MUX=y
> -CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_PROMPT="ns2> "
> -CONFIG_CMD_EEPROM=y
> -CONFIG_CMD_IDE=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_ISO_PARTITION=y
> -CONFIG_EFI_PARTITION=y
> -# CONFIG_PARTITION_UUIDS is not set
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max"
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_USE_ENV_SPI_MAX_HZ=y
> -CONFIG_ENV_SPI_MAX_HZ=20000000
> -CONFIG_ENV_ADDR=0x70000
> -CONFIG_MVSATA_IDE=y
> -# CONFIG_MMC is not set
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_MACRONIX=y
> -CONFIG_MVGBE=y
> -CONFIG_MII=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_KIRKWOOD_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_STORAGE=y
> diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
> deleted file mode 100644
> index ba9301de4d..0000000000
> --- a/configs/netspace_mini_v2_defconfig
> +++ /dev/null
> @@ -1,48 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_DCACHE_OFF=y
> -CONFIG_ARCH_CPU_INIT=y
> -CONFIG_ARCH_KIRKWOOD=y
> -CONFIG_SYS_TEXT_BASE=0x600000
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x70000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_NR_DRAM_BANKS=2
> -CONFIG_IDENT_STRING=" NS v2 Mini"
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
> -CONFIG_BOOTDELAY=3
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=ttyS0,115200"
> -CONFIG_USE_PREBOOT=y
> -CONFIG_CONSOLE_MUX=y
> -CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_PROMPT="ns2> "
> -CONFIG_CMD_EEPROM=y
> -CONFIG_CMD_IDE=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_SF=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_EFI_PARTITION=y
> -# CONFIG_PARTITION_UUIDS is not set
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini"
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_USE_ENV_SPI_MAX_HZ=y
> -CONFIG_ENV_SPI_MAX_HZ=20000000
> -CONFIG_ENV_ADDR=0x70000
> -CONFIG_MVSATA_IDE=y
> -# CONFIG_MMC is not set
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_MACRONIX=y
> -CONFIG_MVGBE=y
> -CONFIG_MII=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_KIRKWOOD_SPI=y
> diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
> deleted file mode 100644
> index 6ba1ef423e..0000000000
> --- a/configs/netspace_v2_defconfig
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_SYS_DCACHE_OFF=y
> -CONFIG_ARCH_CPU_INIT=y
> -CONFIG_ARCH_KIRKWOOD=y
> -CONFIG_SYS_TEXT_BASE=0x600000
> -CONFIG_TARGET_NETSPACE_V2=y
> -CONFIG_ENV_SIZE=0x1000
> -CONFIG_ENV_OFFSET=0x70000
> -CONFIG_ENV_SECT_SIZE=0x10000
> -CONFIG_NR_DRAM_BANKS=2
> -CONFIG_IDENT_STRING=" NS v2"
> -CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
> -CONFIG_BOOTDELAY=3
> -CONFIG_USE_BOOTARGS=y
> -CONFIG_BOOTARGS="console=ttyS0,115200"
> -CONFIG_USE_PREBOOT=y
> -CONFIG_CONSOLE_MUX=y
> -CONFIG_MISC_INIT_R=y
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_HUSH_PARSER=y
> -CONFIG_SYS_PROMPT="ns2> "
> -CONFIG_CMD_EEPROM=y
> -CONFIG_CMD_IDE=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_SF=y
> -CONFIG_CMD_USB=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_DHCP=y
> -CONFIG_CMD_MII=y
> -CONFIG_CMD_PING=y
> -CONFIG_CMD_EXT2=y
> -CONFIG_CMD_FAT=y
> -CONFIG_ISO_PARTITION=y
> -CONFIG_EFI_PARTITION=y
> -# CONFIG_PARTITION_UUIDS is not set
> -CONFIG_OF_CONTROL=y
> -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2"
> -CONFIG_ENV_IS_IN_SPI_FLASH=y
> -CONFIG_USE_ENV_SPI_MAX_HZ=y
> -CONFIG_ENV_SPI_MAX_HZ=20000000
> -CONFIG_ENV_ADDR=0x70000
> -CONFIG_MVSATA_IDE=y
> -# CONFIG_MMC is not set
> -CONFIG_SPI_FLASH=y
> -CONFIG_SPI_FLASH_MACRONIX=y
> -CONFIG_MVGBE=y
> -CONFIG_MII=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_SPI=y
> -CONFIG_KIRKWOOD_SPI=y
> -CONFIG_USB=y
> -CONFIG_USB_EHCI_HCD=y
> -CONFIG_USB_STORAGE=y
> --
> 2.25.1
@@ -35,9 +35,6 @@ config TARGET_KM_KIRKWOOD
bool "KM Kirkwood Board"
select VENDOR_KM
-config TARGET_NETSPACE_V2
- bool "LaCie netspace_v2 Board"
-
config TARGET_IB62X0
bool "ib62x0 Board"
@@ -77,7 +74,6 @@ source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
source "board/keymile/Kconfig"
-source "board/LaCie/netspace_v2/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
deleted file mode 100644
@@ -1,12 +0,0 @@
-if TARGET_NETSPACE_V2
-
-config SYS_BOARD
- default "netspace_v2"
-
-config SYS_VENDOR
- default "LaCie"
-
-config SYS_CONFIG_NAME
- default "lacie_kw"
-
-endif
deleted file mode 100644
@@ -1,14 +0,0 @@
-NETSPACE_V2 BOARD
-M: Simon Guinot <simon.guinot@sequanux.org>
-S: Maintained
-F: board/LaCie/netspace_v2/
-F: include/configs/lacie_kw.h
-F: configs/inetspace_v2_defconfig
-F: configs/netspace_max_v2_defconfig
-F: configs/netspace_v2_defconfig
-
-NETSPACE_LITE_V2 BOARD
-#M: -
-S: Maintained
-F: configs/netspace_lite_v2_defconfig
-F: configs/netspace_mini_v2_defconfig
deleted file mode 100644
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-
-obj-y := netspace_v2.o ../common/common.o
deleted file mode 100644
@@ -1,149 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x00000008 # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
deleted file mode 100644
@@ -1,149 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000DDDD # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 10, Cs0size=512Mb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
deleted file mode 100644
@@ -1,149 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
-#
-# Based on Kirkwood support:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-# Refer doc/README.kwbimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM spi # Boot from SPI flash
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1B1B1B9B
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000618 # DDR Configuration register
-# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
-# bit 4: 0=addr/cmd in smame cycle
-# bit 5: 0=clk is driven during self refresh, we don't care for APX
-# bit 6: 0=use recommended falling edge of clk for addr/cmd
-# bit14: 0=input buffer always powered up
-# bit18: 1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31: 0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
-# bit7-4: TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20: TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
-# bit6-0: TRFC
-# bit8-7: TR2R
-# bit10-9: TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x0000000C # DDR Address Control
-# bit1-0: 00, Cs0width=x8
-# bit3-2: 11, Cs0size=1Gb
-# bit5-4: 00, Cs2width=nonexistent
-# bit7-6: 00, Cs1size =nonexistent
-# bit9-8: 00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16: 0, Cs0AddrSel
-# bit17: 0, Cs1AddrSel
-# bit18: 0, Cs2AddrSel
-# bit19: 0, Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
-# bit0: 0, OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000 # DDR Operation
-# bit3-0: 0x0, DDR cmd
-# bit31-4: 0 required
-
-DATA 0xFFD0141C 0x00000632 # DDR Mode
-# bit2-0: 2, BurstLen=2 required
-# bit3: 0, BurstType=0 required
-# bit6-4: 4, CL=5
-# bit7: 0, TestMode=0 normal
-# bit8: 0, DLL reset=0 normal
-# bit11-9: 6, auto-precharge write recovery ????????????
-# bit12: 0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000004 # DDR Extended Mode
-# bit0: 0, DDR DLL enabled
-# bit1: 1, DDR drive strenght reduced
-# bit2: 1, DDR ODT control lsd enabled
-# bit5-3: 000, required
-# bit6: 1, DDR ODT control msb, enabled
-# bit9-7: 000, required
-# bit10: 0, differential DQS enabled
-# bit11: 0, required
-# bit12: 0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
-# bit2-0: 111, required
-# bit3 : 1 , MBUS Burst Chop disabled
-# bit6-4: 111, required
-# bit7 : 1 , D2P Latency enabled
-# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9 : 0 , no half clock cycle addition to dataout
-# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0 required
-
-DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
-# bit0: 1, Window enabled
-# bit1: 0, Write Protect disabled
-# bit3-2: 00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x07, Size (i.e. 128MB)
-
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
-DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
-# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
-# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
-# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
-# bit3-2: 01, ODT1 active NEVER!
-# bit31-4: zero, required
-
-DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
-# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
-# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
-# bit11-10:1, DQ_ODTSel. ODT select turned on
-
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
deleted file mode 100644
@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <init.h>
-#include <net.h>
-#include <asm/mach-types.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-#include <asm/arch/gpio.h>
-
-#include "netspace_v2.h"
-#include "../common/common.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* Gpio configuration */
- mvebu_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
- NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
-
- /* Multi-Purpose Pins Functionality configuration */
- static const u32 kwmpp_config[] = {
- MPP0_SPI_SCn,
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_GPO, /* Fan speed (bit 1) */
- MPP8_TW_SDA,
- MPP9_TW_SCK,
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO, /* Red led */
- MPP14_GPIO, /* USB fuse */
- MPP16_GPIO, /* SATA 0 power */
- MPP17_GPIO, /* SATA 1 power */
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_SATA1_ACTn,
- MPP21_SATA0_ACTn,
- MPP22_GPIO, /* Fan speed (bit 0) */
- MPP23_GPIO, /* Fan power */
- MPP24_GPIO, /* USB mode select */
- MPP25_GPIO, /* Fan rotation fail */
- MPP26_GPIO, /* USB vbus-in detection */
- MPP28_GPIO, /* USB enable vbus-out */
- MPP29_GPIO, /* Blue led (slow register) */
- MPP30_GPIO, /* Blue led (command register) */
- MPP31_GPIO, /* Board power off */
- MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
- MPP33_GPIO, /* Fan speed (bit 2) */
- 0
- };
- kirkwood_mpp_conf(kwmpp_config, NULL);
-
- return 0;
-}
-
-int board_init(void)
-{
- /* Machine number */
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-
- /* Boot parameters address */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
-
- return 0;
-}
-
-#if defined(CONFIG_MISC_INIT_R)
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
- if (!env_get("ethaddr")) {
- uchar mac[6];
- if (lacie_read_mac_address(mac) == 0)
- eth_env_set_enetaddr("ethaddr", mac);
- }
-#endif
- return 0;
-}
-#endif
-
-#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
-/* Configure and initialize PHY */
-void reset_phy(void)
-{
-#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
- mv_phy_88e1318_init("egiga0", 0);
-#else
- mv_phy_88e1116_init("egiga0", 8);
-#endif
-}
-#endif
-
-#if defined(CONFIG_KIRKWOOD_GPIO)
-/* Return GPIO button status */
-static int
-do_read_button(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
-}
-
-U_BOOT_CMD(button, 1, 1, do_read_button,
- "Return GPIO button status 0=off 1=on", "");
-#endif
deleted file mode 100644
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
- *
- * Based on Kirkwood support:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- */
-
-#ifndef NETSPACE_V2_H
-#define NETSPACE_V2_H
-
-/* GPIO configuration */
-#define NETSPACE_V2_OE_LOW 0x06004000
-#define NETSPACE_V2_OE_HIGH 0x00000031
-#define NETSPACE_V2_OE_VAL_LOW 0x10030000
-#define NETSPACE_V2_OE_VAL_HIGH 0x00000000
-
-#define NETSPACE_V2_GPIO_BUTTON 32
-
-#endif /* NETSPACE_V2_H */
deleted file mode 100644
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x70000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_IDENT_STRING=" IS v2"
-CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_USE_PREBOOT=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ns2> "
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-is2"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
deleted file mode 100644
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x70000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_IDENT_STRING=" NS v2 Lite"
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_USE_PREBOOT=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ns2> "
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2lite"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
deleted file mode 100644
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x70000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_IDENT_STRING=" NS Max v2"
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_USE_PREBOOT=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ns2> "
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2max"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
deleted file mode 100644
@@ -1,48 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x70000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_IDENT_STRING=" NS v2 Mini"
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_USE_PREBOOT=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ns2> "
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2mini"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
deleted file mode 100644
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_DCACHE_OFF=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_KIRKWOOD=y
-CONFIG_SYS_TEXT_BASE=0x600000
-CONFIG_TARGET_NETSPACE_V2=y
-CONFIG_ENV_SIZE=0x1000
-CONFIG_ENV_OFFSET=0x70000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_IDENT_STRING=" NS v2"
-CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200"
-CONFIG_USE_PREBOOT=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_MISC_INIT_R=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="ns2> "
-CONFIG_CMD_EEPROM=y
-CONFIG_CMD_IDE=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-# CONFIG_PARTITION_UUIDS is not set
-CONFIG_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="kirkwood-ns2"
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_USE_ENV_SPI_MAX_HZ=y
-CONFIG_ENV_SPI_MAX_HZ=20000000
-CONFIG_ENV_ADDR=0x70000
-CONFIG_MVSATA_IDE=y
-# CONFIG_MMC is not set
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_MVGBE=y
-CONFIG_MII=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_KIRKWOOD_SPI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y