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[79.14.29.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3d42f884sm226760f8f.57.2026.10.23.07.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 07:56:02 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Brian Masney , Jerome Brunet , Stephen Boyd , Tero Kristo , linux-clk@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH 3/3] clk: ti: dpll: apply the spread spectrum configuration right away Date: Fri, 23 Oct 2026 16:55:32 +0200 Message-ID: <20261023145555.3578469-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261023145555.3578469-1-dario.binacchi@amarulasolutions.com> References: <20261023145555.3578469-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=JX3LofKV; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The spread spectrum clocking (SSC) registers are only programmed by set_rate(), which the clock core skips when the requested rate is already the current one, e.g. when the bootloader has set it up. As a result, the SSC configuration is not applied, as it was with the vendor specific properties. Apply it from set_spread_spectrum() instead, reprogramming the DPLL at its current rate. Signed-off-by: Dario Binacchi --- drivers/clk/ti/dpll3xxx.c | 49 ++++++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 6 deletions(-) diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 634fe0a1f9fd..c181bba2792d 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -690,17 +690,26 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, * @hw: pointer to the clock to set the spread spectrum configuration for * @ss_conf: spread spectrum configuration * - * Stores the spread spectrum clocking (SSC) configuration of the DPLL. The - * configuration is programmed along with the DPLL multiplier and divider - * at the next rate change. The hardware supports center-spread and - * down-spread only. Returns 0 on success, or a negative error value on - * failure. + * Stores the spread spectrum clocking (SSC) configuration of the DPLL and + * applies it right away. The clock framework does not call set_rate() + * when the rate is unchanged, so the current rate is rounded again and + * the DPLL is reprogrammed. If the DPLL is in bypass the configuration is + * applied at the next rate change. Setting again the current + * configuration is a no-op, so that the DPLL is not relocked for nothing + * (e.g. of_clk_set_defaults() runs twice for CLK_OF_DECLARE providers + * that register themselves with of_clk_add_provider()). The hardware + * supports center-spread and down-spread only. Returns 0 on success, or a + * negative error value on failure. */ int omap3_noncore_dpll_set_spread_spectrum(struct clk_hw *hw, const struct clk_spread_spectrum *ss_conf) { struct clk_hw_omap *clk = to_clk_hw_omap(hw); struct dpll_data *dd = clk->dpll_data; + struct clk_spread_spectrum old_conf; + struct clk_rate_request req; + unsigned long rate; + int ret; if (!dd || !dd->ssc_enable_mask) return -EOPNOTSUPP; @@ -718,9 +727,37 @@ int omap3_noncore_dpll_set_spread_spectrum(struct clk_hw *hw, return -EINVAL; } + if (!memcmp(ss_conf, &dd->ssc_conf, sizeof(*ss_conf))) + return 0; + + old_conf = dd->ssc_conf; dd->ssc_conf = *ss_conf; - return 0; + /* In bypass: SSC is programmed along with the next rate change */ + if (clk_hw_get_parent(hw) != dd->clk_ref) + return 0; + + /* Disabling SSC does not need to reprogram the DPLL */ + if (ss_conf->method == CLK_SPREAD_NO) { + omap3_noncore_dpll_ssc_program(clk); + return 0; + } + + rate = clk_hw_get_rate(hw); + clk_hw_init_rate_request(hw, &req, rate); + ret = omap2_dpll_determine_rate(hw, &req); + if (!ret && req.rate != rate) + ret = -EINVAL; + if (!ret) + ret = omap3_noncore_dpll_set_rate(hw, rate, + clk_hw_get_rate(dd->clk_ref)); + if (ret) { + pr_warn("clock: %s: rate %lu can't be kept with SSC enabled\n", + clk_hw_get_name(hw), rate); + dd->ssc_conf = old_conf; + } + + return ret; } /**