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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-4a35a076597sor31830925e9.2.2026.10.28.06.59.21 for (Google Transport Security); Wed, 28 Oct 2026 06:59:21 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AKwUvBwhNjgdh273vTtHu0SpgYK444TyGsCqN6q7jv/HOrokJSrbF7cEO2IShgbMh/Nzf4+pqZya/hDYYmq7gxpS@amarulasolutions.com X-Gm-Gg: AYBFou19TG7oEg8i3CRJXbqNmBeZ1UdKc/VV39u3ROK4YcG1Xn+qwU4PtrMvzGFBQQ4 S7/laNdBfgZG8uBZ4ZN0ej+vCi+vqdGDWTdZOytnNJp94tljDmlAjVA94Db7+X1FSg8quYrp21E HzHAH2vq0LBThEEbuUyGgzAmzWt+RqjDTU9MTcBs6eb60ox7Fe8ogs9AMUKminfkCv5Gb89IhbG 80irC52h1hqvSmK/sIfMqpfXVv8dJbmOP+kBCm6740jl+KhHdvgviivx2gAIUksvaoAFRDsAMjf sgkQZKG10aIKZBXF2S/FPoQQXVH+hbZDCtPSGO/qjeOcILsSv2xMtQ+M3Dvmlbauazt/gBxigNg 6BPEHFIs3AuxjCGEShmbm9N02FzOj5b0BzhsGDnZfNXs7JVcQBYIVpfRZUoU9ZRfa/jnR6N2843 Rk5ITvzGeQpHTmUmPNgbH2fHBzCHDHdQ8jK3caUR4GgazhTVxKMhDdtqKq/r/LGjl9rHpiUeL1F +ZiHKGOsEy5ysQ6fYZQoX+6IJLLW9O5OZ5oRlNq1bMdFUkfj3Ak/X4ZPvRGIzfA1GySyYIxf1q6 NU+YnK0edHc0y+NKaARGqD6hbddgPGflUKk3KhC94guTL6UoQRLmdinxIZ33PG08Qj3Y7CYW2Bf iR/PgTQaFIyVzf0SD2YLXXvTypOb5iV67F2cXuQ/shjzAgdhwQA== X-Received: by 2002:a05:600c:8b05:b0:4a1:fa21:fd90 with SMTP id 5b1f17b1804b1-4a965ec95ebmr53037705e9.9.1793195961149; Wed, 28 Oct 2026 06:59:21 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:20 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 1/4] arm64: dts: st: fix the Engicam RMM RGB display pixel clock Date: Wed, 28 Oct 2026 14:59:05 +0100 Message-ID: <20261028135915.2665857-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ic2QWUrF; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On STM32MP255/257 the LTDC "lcd" clock is a fixed placeholder, since with the LVDS output the pixel clock comes from the LVDS PHY. With the RGB output the pixel clock is instead the LTDC kernel clock (ck_ker_ltdc). Since no consumer references it, the clock is turned off by clk_disable_unused() and its rate is never set. As a result, the LTDC does not run and every commit times out: [CRTC:42:crtc-0] vblank wait timed out [drm] *ERROR* flip_done timed out Use ck_ker_ltdc as "lcd" clock for the RGB panel overlay. Fixes: bc7b07bda4e0 ("arm64: dts: st: support Engicam MicroGEA-STM32MP257D-RMM board") Signed-off-by: Dario Binacchi --- ...2mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso index f89641bdb23b..7be955be58ed 100644 --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso @@ -10,6 +10,7 @@ /dts-v1/; /plugin/; +#include #include #include @@ -35,6 +36,8 @@ touchscreen@38 { }; <dc { + /* RGB output: the pixel clock is the LTDC kernel clock */ + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>;