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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-4a359fdda28sor28412095e9.0.2026.10.28.06.59.25 for (Google Transport Security); Wed, 28 Oct 2026 06:59:25 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AKwUvBws/swMwaANilbPp5IyuxeVQlTuK+MhPPxiXLN3OLMiXy4qSiL7VW35+dDoT6jFxKzlWgqdR8R1tmORVq0W@amarulasolutions.com X-Gm-Gg: AYBFou0Uyo86cfwsyrsydDqNMekYCKu+7a3cf2//VYD6YVxcNZ+WTTxzq2qADfyLaA8 HJZ+qRj6Cvr9yMLQimjjjOq9gvkmmVv3sFmRbdNW0QaNJj9ELvFfpuhdXi3bX2EnT8yQPazsyRQ XkAcZMXL8RrkDWn4G+behIYHAs197L/Pw9AoQQR8FkJo7wnTp/9TRAldJdsIfxR49ZUfHVwhgNb 0kBYDxKBp5xuJiivv1ZJf+aFg3X32g9PAmBNQgX4uYcPJj1ee2br5E6h6CCsWDTI8HBobe2/dQv +IdBRdXXxDXfPhzqkBhja8eSiXfB266Rk7N9DQafWTQmt6dvt/mRT3qckn7/1qo5WRlrmK/S/ai hP2nv+ySwOvhbmUB4tOV8QgoXRlaJeCrv0beo7zm3+5JFa0/EXQm9lMnHy11yzlYxbSijpqeX33 sSi1NHd0SN5pelgPEWOOkaoYKjoPdukIvH3dvw6floiOMej7IEjzx+3jZlCtKSwvvqgK7aRfEeE tC8gWM84SDBZ+v8SvZefXmhEILJENYyuz9fp1Jjezu1Y/LBN0IZ6z/QVx8slxnauPQvhoq6FBF5 PUYXu6rYO1XdY4W3v0+919D6rvlNSfRusC243E+bC8UIBmqlQU7A7iTY5Io/5PTsq8BpRig5i6j a2JQuFINBAPdEzC97XG+aGmqGzg+nJPFu/ARCyGWfARGB6mLK X-Received: by 2002:a05:600c:8b28:b0:4a5:75d2:c104 with SMTP id 5b1f17b1804b1-4a96720304cmr53194255e9.22.1793195964806; Wed, 28 Oct 2026 06:59:24 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:24 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Fabrice Gasnier , Maxime Coquelin , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 3/4] soc: st: stm32mp2-syscfg: register the STM32MP25 clock device Date: Wed, 28 Oct 2026 14:59:07 +0100 Message-ID: <20261028135915.2665857-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b="MIR9k/Pq"; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The STM32MP25 SYSCFG provides the LTDC pixel clock mux, whose driver is an auxiliary driver since the SYSCFG node is bound to this driver. Create the auxiliary device for the clock driver on STM32MP25. Signed-off-by: Dario Binacchi --- drivers/soc/st/Kconfig | 1 + drivers/soc/st/stm32mp2-syscfg.c | 28 ++++++++++++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/soc/st/Kconfig b/drivers/soc/st/Kconfig index 2a9d6a77be45..62bbe8c63238 100644 --- a/drivers/soc/st/Kconfig +++ b/drivers/soc/st/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32MP2 tristate "STM32MP2 SoC family support" depends on ARCH_STM32 || COMPILE_TEST default ARCH_STM32 && ARM64 + select AUXILIARY_BUS select SOC_BUS help If you say yes here, you get support for the ST STM32MP2 family diff --git a/drivers/soc/st/stm32mp2-syscfg.c b/drivers/soc/st/stm32mp2-syscfg.c index 770321a4a6f7..300a949744c5 100644 --- a/drivers/soc/st/stm32mp2-syscfg.c +++ b/drivers/soc/st/stm32mp2-syscfg.c @@ -3,18 +3,42 @@ * Copyright 2026 Marek Vasut */ +#include #include #include #include +#include + +struct stm32mp2_syscfg_data { + bool has_clk; +}; static int stm32mp2_syscfg_probe(struct platform_device *pdev) { - return devm_of_platform_populate(&pdev->dev); + const struct stm32mp2_syscfg_data *data; + struct device *dev = &pdev->dev; + int ret; + + ret = devm_of_platform_populate(dev); + if (ret) + return ret; + + data = device_get_match_data(dev); + if (data && data->has_clk && + !devm_auxiliary_device_create(dev, "clk", NULL)) + return dev_err_probe(dev, -ENODEV, + "failed to register the clock device\n"); + + return 0; } +static const struct stm32mp2_syscfg_data stm32mp25_syscfg_data = { + .has_clk = true, +}; + static const struct of_device_id stm32mp2_syscfg_ids[] = { { .compatible = "st,stm32mp23-syscfg" }, - { .compatible = "st,stm32mp25-syscfg" }, + { .compatible = "st,stm32mp25-syscfg", .data = &stm32mp25_syscfg_data }, { } }; MODULE_DEVICE_TABLE(of, stm32mp2_syscfg_ids);