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[209.85.220.41]) by mx.google.com with SMTPS id 4fb4d7f45d1cf-6507b226e89sor4724973a12.0.2026.01.10.23.33.46 for (Google Transport Security); Sat, 10 Jan 2026 23:33:46 -0800 (PST) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AJvYcCVSvXGEsAxDV97vOjVrFQvt0C4aphDipckLGdsqg+KlaeRlvd2QmGPmf3UUJS94p1IBqTPnHTELCjjaJczN@amarulasolutions.com X-Gm-Gg: AY/fxX77odEQPAJ1Z5f5kENQUQKGzIVfFYsGeeQiKCGfsh+Nk/F7iLWS9LcJiRHUYMp kyjCVF7dqu1kP2VUAqi7VPH9Fhn9iuO5QkHXB5Y9qtqHDiZ2xqK1l4ET28z+ES1Hrie0EKH8nvL 24CyMGpvXrXJU+A2T1AtsQJdfuO+sh65o+JdpMlJoU068j8yvxc9KJryyYJdC7kClZ1jOpnXLHf mqWn4uXGvIHwFcU4wgW6REJObKTjyoqxUuIuH7K87tuuUWG1fcJdZ1G9MmPuBojxkNA7f/eKVIC vSxEd8igejFd81GhYVeW6VWzMeSNO6bMNOD0nShE7+K7pDqMaIUAi7654/bdb16nbPF3Cx+p6wp 3Zp/5YWzNTP3u985qwsGhw3lPJJ4IWl7NtPGSqi+C5Dfu3H0eCji8uL28Q03l5A52KGY6H5vjQs K0N6YfI8YiktozKlhCsdda0vCY3pH1WuPBPkHLD4vYXlHhWYl8FpYp6f9+anBZN7YO50s6JMoqZ ElSkfSjzXwYzUhruB9NMQZBrjYLYqylTYdGlgQ+PhUifHAwyhxa6CsR2w== X-Received: by 2002:a05:6402:2345:b0:649:6ac4:79af with SMTP id 4fb4d7f45d1cf-65097dc62abmr13696924a12.6.1768116825668; Sat, 10 Jan 2026 23:33:45 -0800 (PST) Received: from panicking.homenet.telecomitalia.it (host-87-5-117-220.retail.telecomitalia.it. [87.5.117.220]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507bf6d683sm14548782a12.34.2026.01.10.23.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Jan 2026 23:33:44 -0800 (PST) From: Michael Trimarchi To: Peng Fan , Jaehoon Chung Cc: Tom Rini , Dario Binacchi , u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Michael Trimarchi Subject: [PATCH 1/2] power: regulator: pfuze100: support high voltage range bit Date: Sun, 11 Jan 2026 08:33:38 +0100 Message-ID: <20260111073339.1297089-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260111073339.1297089-1-michael@amarulasolutions.com> References: <20260111073339.1297089-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Hi4h6S7a; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The PFUZE100/200/3000 family of PMICs allow switching regulators (specifically SW2, SW3A/B, SW4 on PFUZE100/200 and SW2 on PFUZE3000) to operate in a "high" voltage range mode. This mode is indicated by a specific bit in the voltage selection register (bit 3 for PFUZE3000, bit 6 for others). When this bit is set: - PFUZE100/200 switches from a 25mV step to a 50mV step, with a different minimum voltage (800mV). - PFUZE3000 SW2 switches to a completely different non-linear voltage table. Currently, the driver uses static descriptors that assume the low/default range. This results in incorrect voltage readings and settings if the PMIC is configured for the high range. This patch updates the driver to: 1. Identify regulators with high-bit support via a new `hi_bit` flag. 2. Read the register during probe to detect the current range configuration. 3. Dynamically update the regulator descriptor (step, mask, min_uV, or table) to match the active range. This aligns the U-Boot driver behavior with the Linux kernel implementation. Signed-off-by: Michael Trimarchi --- drivers/power/regulator/pfuze100.c | 66 ++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 18 deletions(-) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index f864b1d8834..63d39c21bb8 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -18,6 +18,7 @@ * * @name: Identify name for the regulator. * @type: Indicates the regulator type. + * @hi_bit: Indicate if support hi voltage range. * @uV_step: Voltage increase for each selector. * @vsel_reg: Register for adjust regulator voltage for normal. * @vsel_mask: Mask bit for setting regulator voltage for normal. @@ -29,6 +30,7 @@ struct pfuze100_regulator_desc { char *name; enum regulator_type type; + bool hi_bit; unsigned int uV_step; unsigned int vsel_reg; unsigned int vsel_mask; @@ -54,10 +56,11 @@ struct pfuze100_regulator_plat { .voltage = (vol), \ } -#define PFUZE100_SW_REG(_name, base, step) \ +#define PFUZE100_SW_REG(_name, base, step, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .hi_bit = (hbit), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x3F, \ @@ -65,10 +68,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x3F, \ } -#define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \ +#define PFUZE100_SWB_REG(_name, base, mask, step, voltages, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .hi_bit = (hbit), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = (mask), \ @@ -155,15 +159,19 @@ static unsigned int pfuze3000_sw2lo[] = { 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000 }; +static unsigned int pfuze3000_sw2hi[] = { + 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000, +}; + /* PFUZE100 */ static struct pfuze100_regulator_desc pfuze100_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000), - PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000), - PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), + PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, true), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), @@ -176,11 +184,11 @@ static struct pfuze100_regulator_desc pfuze100_regulators[] = { /* PFUZE200 */ static struct pfuze100_regulator_desc pfuze200_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), @@ -195,9 +203,9 @@ static struct pfuze100_regulator_desc pfuze200_regulators[] = { static struct pfuze100_regulator_desc pfuze3000_regulators[] = { PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000), PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000), - PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo), + PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo, true), PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000), @@ -246,9 +254,10 @@ static int pfuze100_regulator_probe(struct udevice *dev) struct dm_regulator_uclass_plat *uc_pdata; struct pfuze100_regulator_plat *plat = dev_get_plat(dev); struct pfuze100_regulator_desc *desc; - int i, size; + int i, size, val, sw_hi = 0x40; + int version = dev_get_driver_data(dev_get_parent(dev)); - switch (dev_get_driver_data(dev_get_parent(dev))) { + switch (version) { case PFUZE100: desc = pfuze100_regulators; size = ARRAY_SIZE(pfuze100_regulators); @@ -260,6 +269,7 @@ static int pfuze100_regulator_probe(struct udevice *dev) case PFUZE3000: desc = pfuze3000_regulators; size = ARRAY_SIZE(pfuze3000_regulators); + sw_hi = 1 << 3; break; default: debug("Unsupported PFUZE\n"); @@ -281,6 +291,26 @@ static int pfuze100_regulator_probe(struct udevice *dev) uc_pdata = dev_get_uclass_plat(dev); uc_pdata->type = desc[i].type; + + /* SW2~SW4 high bit check and modify the voltage value table */ + if (desc[i].hi_bit) { + val = pmic_reg_read(dev->parent, desc[i].vsel_reg); + if (val < 0) { + printf("Fails to read from the register.\n"); + return -EIO; + } + + if (val & sw_hi) { + if (version == PFUZE3000) { + desc[i].volt_table = pfuze3000_sw2hi; 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[87.5.117.220]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507bf6d683sm14548782a12.34.2026.01.10.23.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Jan 2026 23:33:46 -0800 (PST) From: Michael Trimarchi To: Peng Fan , Jaehoon Chung Cc: Tom Rini , Dario Binacchi , u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Michael Trimarchi Subject: [PATCH 2/2] power: regulator: pfuze100: Decouple hardware base voltage from DTS constraints Date: Sun, 11 Jan 2026 08:33:39 +0100 Message-ID: <20260111073339.1297089-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260111073339.1297089-1-michael@amarulasolutions.com> References: <20260111073339.1297089-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=Fd6Z6atE; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently, the driver uses the device tree property `regulator-min-microvolt` (accessed via `uc_pdata->min_uV`) as the base voltage for calculating voltage register values. However, the device tree property defines the safety constraint (the minimum voltage allowed for the specific board/consumer), not the physical minimum voltage the regulator outputs when the selector is at 0. Using the DTS constraint as the linear base leads to incorrect voltage calculations if the constraint does not exactly match the hardware's zero-index voltage. For example, if a regulator physically starts at 700mV but the DTS constrains it to 1000mV, the driver incorrectly calculates the selector assuming 0 corresponds to 1000mV. Fix this by: 1. Adding a `min_uV` field to the regulator descriptor to hold the true hardware base voltage as defined in the datasheet. 2. Updating the regulator definitions with the correct base voltages (aligned with Linux kernel driver definitions). 3. Using the descriptor's hardware minimum for all voltage-to-selector calculations, instead of the DTS constraint. 4. Adding a validation check to ensure the DTS constraint is within the hardware's possible range. Signed-off-by: Michael Trimarchi --- drivers/power/regulator/pfuze100.c | 94 ++++++++++++++++-------------- 1 file changed, 51 insertions(+), 43 deletions(-) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 63d39c21bb8..107f036d33f 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -32,6 +32,7 @@ struct pfuze100_regulator_desc { enum regulator_type type; bool hi_bit; unsigned int uV_step; + unsigned int min_uV; unsigned int vsel_reg; unsigned int vsel_mask; unsigned int stby_reg; @@ -54,13 +55,15 @@ struct pfuze100_regulator_plat { .name = #_name, \ .type = REGULATOR_TYPE_FIXED, \ .voltage = (vol), \ + .min_uV = (vol), \ } -#define PFUZE100_SW_REG(_name, base, step, hbit) \ +#define PFUZE100_SW_REG(_name, base, min, step, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ .hi_bit = (hbit), \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x3F, \ @@ -88,10 +91,11 @@ struct pfuze100_regulator_plat { .volt_table = (voltages), \ } -#define PFUZE100_VGEN_REG(_name, base, step) \ +#define PFUZE100_VGEN_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_LDO, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = 0xF, \ @@ -99,10 +103,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x20, \ } -#define PFUZE3000_VCC_REG(_name, base, step) \ +#define PFUZE3000_VCC_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_LDO, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = 0x3, \ @@ -110,10 +115,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x20, \ } -#define PFUZE3000_SW1_REG(_name, base, step) \ +#define PFUZE3000_SW1_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x1F, \ @@ -121,10 +127,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x1F, \ } -#define PFUZE3000_SW2_REG(_name, base, step) \ +#define PFUZE3000_SW2_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x7, \ @@ -132,10 +139,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x7, \ } -#define PFUZE3000_SW3_REG(_name, base, step) \ +#define PFUZE3000_SW3_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0xF, \ @@ -165,55 +173,55 @@ static unsigned int pfuze3000_sw2hi[] = { /* PFUZE100 */ static struct pfuze100_regulator_desc pfuze100_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), - PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, false), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), - PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, true), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 300000, 25000, false), + PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 300000, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 400000, 25000, true), + PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 400000, 25000, true), PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), - PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), - PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000), - PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000), - PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000), - PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000), - PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000), + PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 1800000, 100000), }; /* PFUZE200 */ static struct pfuze100_regulator_desc pfuze200_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 300000, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 400000, 25000, true), PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), - PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), - PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000), - PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000), - PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000), - PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000), - PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000), + PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 1800000, 100000), }; /* PFUZE3000 */ static struct pfuze100_regulator_desc pfuze3000_regulators[] = { - PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000), - PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000), + PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 700000, 25000), + PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 700000, 25000), PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo, true), - PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000), + PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 900000, 50000), PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), - PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000), - PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000), - PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000), - PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000), - PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000), - PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000), + PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 800000, 50000), + PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 2850000, 150000), + PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 2850000, 150000), + PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 1800000, 100000), }; #define MODE(_id, _val, _name) { \ @@ -483,15 +491,15 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) val &= desc->vsel_mask; *uV = desc->volt_table[val]; } else { - if (uc_pdata->min_uV < 0) { - debug("Need to provide min_uV in dts.\n"); + if (uc_pdata->min_uV < desc->min_uV) { + debug("min_uV in dts can not be below regulator min_uV.\n"); return -EINVAL; } val = pmic_reg_read(dev->parent, desc->vsel_reg); if (val < 0) return val; val &= desc->vsel_mask; - *uV = uc_pdata->min_uV + (int)val * desc->uV_step; + *uV = desc->min_uV + (int)val * desc->uV_step; } return 0; @@ -513,13 +521,13 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) return pmic_clrsetbits(dev->parent, desc->vsel_reg, desc->vsel_mask, i); } else { - if (uc_pdata->min_uV < 0) { - debug("Need to provide min_uV in dts.\n"); + if (uc_pdata->min_uV < desc->min_uV) { + debug("min_uV in dts can not be below regulator min_uV.\n"); return -EINVAL; } return pmic_clrsetbits(dev->parent, desc->vsel_reg, desc->vsel_mask, - (*uV - uc_pdata->min_uV) / desc->uV_step); + (*uV - desc->min_uV) / desc->uV_step); } return 0;