From patchwork Sun Jan 11 08:23:46 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 4428 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ej1-f71.google.com (mail-ej1-f71.google.com [209.85.218.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 55A583F1D4 for ; Sun, 11 Jan 2026 09:23:58 +0100 (CET) Received: by mail-ej1-f71.google.com with SMTP id a640c23a62f3a-b844098869csf538033866b.2 for ; Sun, 11 Jan 2026 00:23:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1768119838; cv=pass; d=google.com; s=arc-20240605; b=AvF0BmBDWwjg1h52gYs9jFBoNb6mVf/V6Qu5y3QvHxNOro3VZfJGpo459moOKjXDHs cC08gebHDswSwh57y2WqEqMjU31YsTi6u9spvxOI2XUAYO3zl4dyPzXSGjV536VAqIBn PMg1AeYKG1X0hFuGEXp0OzWw8I+3bJ57KDkFSCjAChyrr/D/jevaRlBDpEGxHdZatmiB /YyvBVU3fwYOSTu9Vh7HJ+fvv95MSm6jeCHXxZBPjbydX36aWxLJ7iTDpUauOlvnGVSW 3nhwLywnlbTZUXs7pb1/wDSZ6zslF2yHQ5KQfGPfr8d9TlGKUTgtw9tzu8O4nZ0ZTYjt nZqQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/qOfr70YksQH1cDk8twanAQNrfagx1hWsmHP1goZnz4=; fh=6pOQyucNLgrQrvV7fY2DLW271MLlb4Ypkn32/W7AkdI=; b=I0TQAgyO9a1JmLd9IDXsBKuiWOrJpyskC71SGok7it08FOCnOS1vJy/zqp9ikqUByr zYP49Wq2WjGs3AOxnrRVArAPSjPxJEOslX5HhYFXXNfffW3P2hhoV73ltPH6wualvbD9 XSAnrQVcbllEe9809UUUvKDD8WxTs8Io3u7e2qYqD3lT3WSCwteryTtbeaW8CjTEh4TJ XmnzKxAENT/fGvXAa9sxVMB6OVrV8e/v/vP+EJjTNRyRoDEXgV6gQcFtdKyaMZF3xxc2 AmY0qH23mWhgYqFGak7FrjwfM1+CU5k4ODpr3CrCW9L8hj9LnACfQyTRyknYs4AcU5G8 1bVA==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IE59pOBk; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1768119838; x=1768724638; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=/qOfr70YksQH1cDk8twanAQNrfagx1hWsmHP1goZnz4=; b=Hy8GT0jN4uDhyaEKa6jBLhvvo4wTSkMaW2336pPxavlNyy8/YYSDh0muh4ekeuqoZI NctI6lu33ghAqHRO99bBXs7ZE4K9q0SyoXuapzwENgYYZSESYtUISljpKVpmGQnOzzzO 4mZncKIdvyumEbI/Mn0ZcDwVH+yPq9sRzpMSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768119838; x=1768724638; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/qOfr70YksQH1cDk8twanAQNrfagx1hWsmHP1goZnz4=; b=YiW2OAX1XqopRBS32nekBySjVktPs+ihCa4eTGF8I7XJpYglQi0A/Og6MY9jQHkQ98 OVmlASmvQ0YB2kl7MyZhsay6xLtR4UE2crLk4jdodc3PbbDl+qhyIf754opYMToG3n62 GcXM4Ml41SINf8dQvPsbGdmPsxVnJv0NlypNafz3M6Frrs9KobcFenM7gTi+0oZHCA/F EqRYIUPJnBMGz/8xIrB0+L/QZsMDTCixxR/8tv48dfBL3s1TSEvx/QIvffotJUfEEBUH JG/I2bAq/axG9LqkIUi2OxQRZ0fJhgSMdgKRn3pSP9VZtgVapcItqQ1sGrP0NQNJrrEJ 7WRw== X-Forwarded-Encrypted: i=2; AJvYcCWZM0lau0pT7n2RlBIQysQIZke8ZqHkSJk03ndyTMF7Fxou1xOn5fngdDaWrSF60DMCJuTaQjiVINrAWeln@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0Yz4Aqd/OgJlIYbxuhSpqSAEh58IYF35pM4bciW6AOzqrekUMeRa JRsLpyKJjpqo3RT4+RAGQTC4VpbmwzZWSR1DtaumMjXtzrE4mDuoshgePC2aV4jlX72+Rw== X-Google-Smtp-Source: AGHT+IF9K6GCPpfwbS+tfwtrKJhwkldI6ppqPYXKul+giJfBV9SCqRetM5SdX4gmOBBPqPRwW8RFxw== X-Received: by 2002:a17:907:9603:b0:b80:a31:eb08 with SMTP id a640c23a62f3a-b84450205e1mr1428509966b.55.1768119837850; Sun, 11 Jan 2026 00:23:57 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com; h="AV1CL+Ed8EWTIZigudsI0pLs0lrTyZ+5cdhROuryrGnPOtcfpQ==" Received: by 2002:aa7:dd06:0:b0:64c:7925:f275 with SMTP id 4fb4d7f45d1cf-650748d4084ls5284112a12.1.-pod-prod-09-eu; Sun, 11 Jan 2026 00:23:55 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCX+wbfKBlQMow4Yq851oYVqAxQJ/EMVBpyYHaCWaC7HKgc4VL/t/UYEqx7quTn0dncLwpXcKZWutJusFttl@amarulasolutions.com X-Received: by 2002:a17:907:728a:b0:b87:1064:4ea1 with SMTP id a640c23a62f3a-b8710645888mr82020266b.65.1768119835536; Sun, 11 Jan 2026 00:23:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1768119835; cv=none; d=google.com; s=arc-20240605; b=ZUxrcK07wfU1Byey1uqdhfUdS+iJ6a68pGu6ScdmWWOOGqxOq2fp5bYpfhPRbiTnC0 nRD8aAFaHpsm6DYZVNesds9gnVeI8DL3hKdsfkfKQhUxrThJqElDaqYAcjHLpHg11ujt aIWnDIUc8bWaLxFswRIvSwWvtNHLWdOs9Wj0FkJeTZTgY5SG9pp2t/Dyl0dmQMsVFdoZ zUAzZeat9Byb7yPKNd7qdhDKiPQu1AaUwH0HOv/Xogk23J9yiMAuV/kXUvzGYAsPqFBm zp3qtuBcC0/Ll/rSUo/TA8CEltBWroR2Mu9k0C9681dKlDOIlBkQgYQnDFpFf0nUG8cC lI6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dtgzZWNyxrestrdjMq7Z3/mtKELvM+5iu53N1RBbkB4=; fh=lQ5X/UrhkUps7XI/GGqJHoNTBfFzUaclzNK5T3SKrSQ=; b=cmBujVu4cvi8YTxPLgs9+o7HmlcGvdkcoszjXt4AonR1qGH7a/TduOH3EwrKMkjeOT EY2Jts7jWRKDMzoSVyUTH3RRvJUKYoivko6oRdAwsBb3htk3dQyp2Fpqcq2ykVGsg5j7 zQXBS1O/TDBT6S2ZW7Hi8TqyWvr9bHAZg+4Z9bdcNNmLpqOicPgB2cuXPbxGZAZlgSec d3CchERGT6ELYAU2oh2iAVRL8h+Ji0Yp/AJ+ndaY+FpSy9DBN+MN1H3REbf4LNfduu7q cxOFHfCKFC4AtD4AhZPM/tD+NEIluEh6AKlQOqQE6A5LFDyzY0nf68OxADJW7u/fePav wi8g==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IE59pOBk; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id 4fb4d7f45d1cf-6507c06a654sor3550916a12.15.2026.01.11.00.23.55 for (Google Transport Security); Sun, 11 Jan 2026 00:23:55 -0800 (PST) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AJvYcCVLftlGEjduh7Zn3LwzJ5rFLfnTHRdZMgzwXJ4X3iLQSmkTtZl2oi4rBit9aDreCuBi85Bxe+T8eWFJuqsp@amarulasolutions.com X-Gm-Gg: AY/fxX556t/HBy0lkWILzdm0iaQjG+kUjMNJpFbREjRhEIXlbGEHmemVJ/udd31dHHa tFTTwtOy2rvoOpF8gOxSdHO7GAAvtrUxIm24O/si7jiGrJ4JutFcUx163uvJwIEIFR1meTxwGl6 v0zyyt9nzd6mY81guV3YIE9TISsKJeQnd2g4KHUAdwShUqxmuAZccfb6q0Q7Kw6iWrCbD+EGDlJ BJLudo47KLtQ+EuLP9QO858N1N71JrR88m/AHR7i5QNMlAZUKRuZ7+C3kLv27K8yXgXK3FZDhI4 EvzAQwOmqhRO7Hzc0XrXuQ04CUZBSQFtgUjQ5wHrOxOs1tn8B9ELA9nmxsQfLdo3khUf35i7KE+ gAPoOCuu1ZA3vY9fplbQq6R18BEWZxD+8QXIvHM2WcZMPDmFPdvdnQWCgla2TCR1aTAWmBdQjhZ I82tDzpXSCKRrhdmnvViM49WsCzhAMMYx1eRPYj58NoWFtkrh64ujEeCTbItDK2TyC1cv5Pu7i2 AudcGXw9T+S2rKcJbiXlwcDwd5sE4xLdU1IPUAIpuHP0bYlhuwRjc8WzQ== X-Received: by 2002:a05:6402:26d1:b0:64b:5f4e:9e6d with SMTP id 4fb4d7f45d1cf-65097e50c56mr13244155a12.18.1768119835009; Sun, 11 Jan 2026 00:23:55 -0800 (PST) Received: from panicking.homenet.telecomitalia.it (host-87-5-117-220.retail.telecomitalia.it. [87.5.117.220]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507b9d44bfsm14608346a12.8.2026.01.11.00.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 00:23:54 -0800 (PST) From: Michael Trimarchi To: Peng Fan , Jaehoon Chung Cc: Tom Rini , Dario Binacchi , u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Michael Trimarchi Subject: [PATCH V2 1/2] power: regulator: pfuze100: support high voltage range bit Date: Sun, 11 Jan 2026 09:23:46 +0100 Message-ID: <20260111082347.1302003-2-michael@amarulasolutions.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260111082347.1302003-1-michael@amarulasolutions.com> References: <20260111082347.1302003-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=IE59pOBk; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The PFUZE100/200/3000 family of PMICs allow switching regulators (specifically SW2, SW3A/B, SW4 on PFUZE100/200 and SW2 on PFUZE3000) to operate in a "high" voltage range mode. This mode is indicated by a specific bit in the voltage selection register (bit 3 for PFUZE3000, bit 6 for others). When this bit is set: - PFUZE100/200 switches from a 25mV step to a 50mV step, with a different minimum voltage (800mV). - PFUZE3000 SW2 switches to a completely different non-linear voltage table. Currently, the driver uses static descriptors that assume the low/default range. This results in incorrect voltage readings and settings if the PMIC is configured for the high range. This patch updates the driver to: 1. Identify regulators with high-bit support via a new `hi_bit` flag. 2. Read the register during probe to detect the current range configuration. 3. Dynamically update the regulator descriptor (step, mask, min_uV, or table) to match the active range. This aligns the U-Boot driver behavior with the Linux kernel implementation. Signed-off-by: Michael Trimarchi --- V1->V2: drop change of uv_mask, it's already fixed for bit 6 and anyway 0x7 was invalid --- drivers/power/regulator/pfuze100.c | 65 +++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 18 deletions(-) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index f864b1d8834..2242bf68f39 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -18,6 +18,7 @@ * * @name: Identify name for the regulator. * @type: Indicates the regulator type. + * @hi_bit: Indicate if support hi voltage range. * @uV_step: Voltage increase for each selector. * @vsel_reg: Register for adjust regulator voltage for normal. * @vsel_mask: Mask bit for setting regulator voltage for normal. @@ -29,6 +30,7 @@ struct pfuze100_regulator_desc { char *name; enum regulator_type type; + bool hi_bit; unsigned int uV_step; unsigned int vsel_reg; unsigned int vsel_mask; @@ -54,10 +56,11 @@ struct pfuze100_regulator_plat { .voltage = (vol), \ } -#define PFUZE100_SW_REG(_name, base, step) \ +#define PFUZE100_SW_REG(_name, base, step, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .hi_bit = (hbit), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x3F, \ @@ -65,10 +68,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x3F, \ } -#define PFUZE100_SWB_REG(_name, base, mask, step, voltages) \ +#define PFUZE100_SWB_REG(_name, base, mask, step, voltages, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .hi_bit = (hbit), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = (mask), \ @@ -155,15 +159,19 @@ static unsigned int pfuze3000_sw2lo[] = { 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000 }; +static unsigned int pfuze3000_sw2hi[] = { + 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000, +}; + /* PFUZE100 */ static struct pfuze100_regulator_desc pfuze100_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000), - PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000), - PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), + PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, true), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), @@ -176,11 +184,11 @@ static struct pfuze100_regulator_desc pfuze100_regulators[] = { /* PFUZE200 */ static struct pfuze100_regulator_desc pfuze200_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), @@ -195,9 +203,9 @@ static struct pfuze100_regulator_desc pfuze200_regulators[] = { static struct pfuze100_regulator_desc pfuze3000_regulators[] = { PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000), PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000), - PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo), + PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo, true), PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000), - PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst), + PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000), @@ -246,9 +254,10 @@ static int pfuze100_regulator_probe(struct udevice *dev) struct dm_regulator_uclass_plat *uc_pdata; struct pfuze100_regulator_plat *plat = dev_get_plat(dev); struct pfuze100_regulator_desc *desc; - int i, size; + int i, size, val, sw_hi = 0x40; + int version = dev_get_driver_data(dev_get_parent(dev)); - switch (dev_get_driver_data(dev_get_parent(dev))) { + switch (version) { case PFUZE100: desc = pfuze100_regulators; size = ARRAY_SIZE(pfuze100_regulators); @@ -260,6 +269,7 @@ static int pfuze100_regulator_probe(struct udevice *dev) case PFUZE3000: desc = pfuze3000_regulators; size = ARRAY_SIZE(pfuze3000_regulators); + sw_hi = 1 << 3; break; default: debug("Unsupported PFUZE\n"); @@ -281,6 +291,25 @@ static int pfuze100_regulator_probe(struct udevice *dev) uc_pdata = dev_get_uclass_plat(dev); uc_pdata->type = desc[i].type; + + /* SW2~SW4 high bit check and modify the voltage value table */ + if (desc[i].hi_bit) { + val = pmic_reg_read(dev->parent, desc[i].vsel_reg); + if (val < 0) { + printf("Fails to read from the register.\n"); + return -EIO; + } + + if (val & sw_hi) { + if (version == PFUZE3000) { + desc[i].volt_table = pfuze3000_sw2hi; + } else { + desc[i].uV_step = 50000; + uc_pdata->min_uV = 800000; + } + } + } + if (uc_pdata->type == REGULATOR_TYPE_BUCK) { if (!strcmp(dev->name, "swbst")) { uc_pdata->mode = pfuze_swbst_modes; From patchwork Sun Jan 11 08:23:47 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Nazzareno Trimarchi X-Patchwork-Id: 4429 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 235813F1D4 for ; Sun, 11 Jan 2026 09:24:01 +0100 (CET) Received: by mail-ed1-f69.google.com with SMTP id 4fb4d7f45d1cf-64d18dbff2asf7032331a12.0 for ; Sun, 11 Jan 2026 00:24:01 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1768119841; cv=pass; d=google.com; s=arc-20240605; b=YrDPxl9Vp9FpoM6v0djqMRWs4glV6+55hi/zVE6/SKoJRvJmlh3uyq64NVhFwbJhzH OM18Lg8OmtrbhspWJ1Ly2W+VXwqPo6ZNLulsvcP92jarcHmqSfnKtnesXxyq5u5nwbFG Ox8Re1O5Gs6j3CAyDYGVBzT10SPQa5ExNCs5Sp/abx+n1J6lWd8RJm+irnTr/vA8dUDL XWaswRIC7vfxbojjMxGWt0+WcIMzjw24X+1KuyCOWQXf1riUK7HyWHLV4Nz6kVUEKHdB 2+wTVmOPs2aSUq+7nA83BCebi9yHLu3DCkuXhHTX9HAwDo+omr0q909+7fLWcFPFtioc 0nHQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Awl0gqKeniLyPH0JyQ4gsniYRM2BKqACxl47Ix6R0bw=; fh=TmmJP6kYrf1ZeInk+0xBjf9obUgQeqOO0Be6YZctcpk=; b=lUpqHxuAZflboQAVUDCmmNgbn+9dcJVrcvqHty0x2KLY54RcolSK271Zr0w0y6aynU ccFIU45pz6PbRv98p07eani6DA/gT1T59RbFxRGo7rlq4xvItT/iEGVdbnjRYRtxvNuz KE1ffxJEqEUxiQELcbwfTCcgD6lCUx7dLXI16m23Nh9u3rtrnehKyujOpXKJztbNDm9t VRkVteL7vgNmP3xG3jsEj+VfH59SaVLD0J8ze6hpyjwvfZemf+b0Pb04G/GnupuRDb0Z M9FXLg+7yy8rleEHjUS+temhcXYrbSBZeHwmrJhJFD43GNvZrvVWMOQDDUH1Yy3zPJnJ W72A==; darn=patchwork.amarulasolutions.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pdDbVKA4; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1768119841; x=1768724641; darn=patchwork.amarulasolutions.com; h=list-unsubscribe:list-archive:list-help:list-post:list-id :mailing-list:precedence:x-original-authentication-results :x-original-sender:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to; bh=Awl0gqKeniLyPH0JyQ4gsniYRM2BKqACxl47Ix6R0bw=; b=HGrxgbhIjsMe/SNlUE0Fxt9tDOPK0W8sGJbs5sGD/9UvzpgfQtPrDIaTywVqxnL7gO +1rHL/8uYC5X7pzWFUBxsM+j0NXFNrRE9FVDhPFVSkvYw7NC+SI1rvuCklxco6CNyE8c GmDhWnhawQ/8TNPOh8/hpq2Hc2OtPQZG4S5IQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768119841; x=1768724641; h=list-unsubscribe:list-archive:list-help:list-post :x-spam-checked-in-group:list-id:mailing-list:precedence :x-original-authentication-results:x-original-sender:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-beenthere:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Awl0gqKeniLyPH0JyQ4gsniYRM2BKqACxl47Ix6R0bw=; b=EsJtmhSQr5zmctZn++cwHQfJYZRDZkl3cI0TouuINKTxpHbigYB+YRT0tKoamj1FvT G9Am57LoYPPc4IbCaIf+7S30oqivwY8w/i16SLVjmH035znh4NCtvJaQk9HPT9ZgjVtU MLNhTzCA8FYuFQI/JMMzS0j55JVsmTENsLQNblSA1vb0u80AVTSIPaUPbwx5B/flb/XM YeKUfNBUFACAhTPzYLQVPjtaaCQhbfxhut3XvrD3KyQ3DEZKTVWHLxf71Fq0UCTSJFWU M41M4mVoqvUEJ59xZzXtLGKqBM166yidda2Gt1ke1Q5bpj3ORTlYAekmGD92cTY7qnqC EjYQ== X-Forwarded-Encrypted: i=2; AJvYcCX7dFiQLfXHyGwyLjFaC4MoyXFwjWS2WdHqMT7A/CSbenrglNItGmeQO1qmovymGOZa+fCAHEssBawHsYtQ@patchwork.amarulasolutions.com X-Gm-Message-State: AOJu0YxGf4BT6eXKK243tn0jguIJPJcB2GHnrznMxXyZHFyqoX7oTRXV dLxtzIVyfi76BoCHFqWsJWoMAItKBlk5SkUp2igTASCUDhaZUeAb1geYtjMTZSu5utJUxQ== X-Google-Smtp-Source: AGHT+IGFuG0ap4mcpH2jF5esE5H49P7aw6DZ7rTBCq2RSIP2HCHjbCwigTo4cfCd9jSKlSZN9z3YCw== X-Received: by 2002:a05:6402:1441:b0:64d:f39:3fdb with SMTP id 4fb4d7f45d1cf-65097decaf2mr14644098a12.13.1768119840736; Sun, 11 Jan 2026 00:24:00 -0800 (PST) X-BeenThere: linux-amarula@amarulasolutions.com; h="AV1CL+FcPrvGJM4tpeUklzvm3itP4IiiJ6RcL/dTpu4rPQveGg==" Received: by 2002:aa7:c487:0:b0:64d:faf4:f73e with SMTP id 4fb4d7f45d1cf-650743340b5ls4904355a12.0.-pod-prod-05-eu; Sun, 11 Jan 2026 00:23:58 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCU4TA6q4r66x1pSQ7A1/307Lzd9LeK0cyXPb+awzPSAtIBVSuORxMMSTABqqQdYdCR0aAa0mFt0DZ8YuUwN@amarulasolutions.com X-Received: by 2002:a17:907:70c:b0:b54:7778:c62d with SMTP id a640c23a62f3a-b84451adc5bmr1342955166b.15.1768119838220; Sun, 11 Jan 2026 00:23:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1768119838; cv=none; d=google.com; s=arc-20240605; b=TzkE4WrzZEhKUoPYqaEfrTjjVCRAPDXcSkk2Z4vB1kXTHMDA8eQ2Rd1XzOCLUDCAe3 YYSKqE5ZPMxBAfavdcas4Zt14rQeHMu+GJ522eM36FxTCkz7yZvnDUykBjMiEkJ/brvS kAAxhfsnwdCbBNJ5BKN4uJ3Wd7CUYAI7C26BkWtSWkwzhU11iH7Cna8pMFEdrJ/oXzwU LaSucERCX0SrM1B0FlYWJ1eBzjzUagpwVUVnnTh5Sgq3yx9jTWfjjTwLMHzkjVKTZbzq lrIRJ7oIFgKJtKwZHxpAAOJwL6mDG6cP0kdcy4HBHBu9w4zhTeDGR+IuFh/mrz53XnFv cpAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Q+9SRMItVtFRbxoOe6HUwMhSYuK6V3Az7ye8RRjpMAw=; fh=QmHWHPluvtFq1Fbo3Z7pSBzFSwBOwBX0MyrH0ThWWn0=; b=AlsHAXDGVDLrQbhI92To9ZmfkkhmtwOp5SFCFWkr1X3fnygs/svdMsc4xFY91wE5+5 auxtPOJI407HlIv2NadhImeiGW5Wvrks+iKDSGor1dEmHX5sZ/Stmwq6/65ZsELjH1B4 iigzVBZxGzgniuxUNBYmIt+3VlrSo0fPPtD/NtY6sAS7xRzwB8zaZGUFtqVMXwGNVaFT tbJ+lGiirELho0lopF/f+JpVLvdXbvrvk7vxXAec/uFLkS0Wtl5ZsUKJwP+nve5xNN/x RoaCsBGeT7XIthU4vzGLGjazvbJ8MOyInYiOOz+DnRnYawy2sFN6SY702mKWkdGxPhyf 11hQ==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pdDbVKA4; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Received: from mail-sor-f41.google.com (mail-sor-f41.google.com. [209.85.220.41]) by mx.google.com with SMTPS id a640c23a62f3a-b86ff87bb41sor44099366b.12.2026.01.11.00.23.58 for (Google Transport Security); Sun, 11 Jan 2026 00:23:58 -0800 (PST) Received-SPF: pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AJvYcCWUvldK3KZh8vYbFWKuJHgs8NpQSTcNCtJM1sMf3rpWs7tuvOZeVr1VjeMzoBxocteaENMpdhFDMpjQ5EoI@amarulasolutions.com X-Gm-Gg: AY/fxX41og5g1MJHOBCWPgNhgkFi1Ts7kMzefOrp/AdW1zODZstIjDY/YHZ/vpJAvzn gBcGb3coIz8+Foqdc579TMfKt2oHItZSGts8i8JhQnuaHiIDESqfYze1KkkoDi3tlJZFwu4C4Cq +ZRF2g2WI3QX9mHshF4xF2yO3q7u5Zv4Up0fx1Ni654ojXKNbZy+Zj7YAypxzjpUvTlQ9vQfAdF wLwb0AlBcuujkfOSFX0aWTCyHeWN1pnXcah0Om1BwKhrjDJZnv2MPVzw5UYnri9rCI7Y+Jxcmo+ QX+Jcs8d8+3Nv39qCitd6Z0uWOSdqiWvmNfr5mPMVRV9GFMGDZ3ndbCFpiOcfxIUvmLWNZzfMOa r9a3MWOalz22ttIK8EGspbGb22In1OlTakGadt4oZsO6HpzDFGHOaAGoi99jfK0tsF3QzJpS9Gg MxBtCK1aJSjEu//GMjR+G474bFP1FXbzbrE6V7Nhyeov/luesbLy6MwfEat84dyFaG9dVvP9KW7 /S+q/bC3KEcP7AJwGxpFIX8SAs0ZZh6nR+9lMYwJeQXyzSLRITwU4lE4qNOYkl0hmt6 X-Received: by 2002:a17:907:70c:b0:b54:7778:c62d with SMTP id a640c23a62f3a-b84451adc5bmr1342953066b.15.1768119837553; Sun, 11 Jan 2026 00:23:57 -0800 (PST) Received: from panicking.homenet.telecomitalia.it (host-87-5-117-220.retail.telecomitalia.it. [87.5.117.220]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6507b9d44bfsm14608346a12.8.2026.01.11.00.23.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jan 2026 00:23:56 -0800 (PST) From: Michael Trimarchi To: Peng Fan , Jaehoon Chung Cc: Tom Rini , Dario Binacchi , u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Michael Trimarchi Subject: [PATCH V2 2/2] power: regulator: pfuze100: Decouple hardware base voltage from DTS constraints Date: Sun, 11 Jan 2026 09:23:47 +0100 Message-ID: <20260111082347.1302003-3-michael@amarulasolutions.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260111082347.1302003-1-michael@amarulasolutions.com> References: <20260111082347.1302003-1-michael@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: michael@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=pdDbVKA4; spf=pass (google.com: domain of michael@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=michael@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Content-Type: text/plain; charset="UTF-8" Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Currently, the driver uses the device tree property `regulator-min-microvolt` (accessed via `uc_pdata->min_uV`) as the base voltage for calculating voltage register values. However, the device tree property defines the safety constraint (the minimum voltage allowed for the specific board/consumer), not the physical minimum voltage the regulator outputs when the selector is at 0. Using the DTS constraint as the linear base leads to incorrect voltage calculations if the constraint does not exactly match the hardware's zero-index voltage. For example, if a regulator physically starts at 700mV but the DTS constrains it to 1000mV, the driver incorrectly calculates the selector assuming 0 corresponds to 1000mV. Fix this by: 1. Adding a `min_uV` field to the regulator descriptor to hold the true hardware base voltage as defined in the datasheet. 2. Updating the regulator definitions with the correct base voltages (aligned with Linux kernel driver definitions). 3. Using the descriptor's hardware minimum for all voltage-to-selector calculations, instead of the DTS constraint. 4. Adding a validation check to ensure the DTS constraint is within the hardware's possible range. Signed-off-by: Michael Trimarchi --- V1->V2: no changes --- drivers/power/regulator/pfuze100.c | 94 ++++++++++++++++-------------- 1 file changed, 51 insertions(+), 43 deletions(-) diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c index 63d39c21bb8..107f036d33f 100644 --- a/drivers/power/regulator/pfuze100.c +++ b/drivers/power/regulator/pfuze100.c @@ -32,6 +32,7 @@ struct pfuze100_regulator_desc { enum regulator_type type; bool hi_bit; unsigned int uV_step; + unsigned int min_uV; unsigned int vsel_reg; unsigned int vsel_mask; unsigned int stby_reg; @@ -54,13 +55,15 @@ struct pfuze100_regulator_plat { .name = #_name, \ .type = REGULATOR_TYPE_FIXED, \ .voltage = (vol), \ + .min_uV = (vol), \ } -#define PFUZE100_SW_REG(_name, base, step, hbit) \ +#define PFUZE100_SW_REG(_name, base, min, step, hbit) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ .hi_bit = (hbit), \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x3F, \ @@ -88,10 +91,11 @@ struct pfuze100_regulator_plat { .volt_table = (voltages), \ } -#define PFUZE100_VGEN_REG(_name, base, step) \ +#define PFUZE100_VGEN_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_LDO, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = 0xF, \ @@ -99,10 +103,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x20, \ } -#define PFUZE3000_VCC_REG(_name, base, step) \ +#define PFUZE3000_VCC_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_LDO, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base), \ .vsel_mask = 0x3, \ @@ -110,10 +115,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x20, \ } -#define PFUZE3000_SW1_REG(_name, base, step) \ +#define PFUZE3000_SW1_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x1F, \ @@ -121,10 +127,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x1F, \ } -#define PFUZE3000_SW2_REG(_name, base, step) \ +#define PFUZE3000_SW2_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0x7, \ @@ -132,10 +139,11 @@ struct pfuze100_regulator_plat { .stby_mask = 0x7, \ } -#define PFUZE3000_SW3_REG(_name, base, step) \ +#define PFUZE3000_SW3_REG(_name, base, min, step) \ { \ .name = #_name, \ .type = REGULATOR_TYPE_BUCK, \ + .min_uV = (min), \ .uV_step = (step), \ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ .vsel_mask = 0xF, \ @@ -165,55 +173,55 @@ static unsigned int pfuze3000_sw2hi[] = { /* PFUZE100 */ static struct pfuze100_regulator_desc pfuze100_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), - PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 25000, false), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), - PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 25000, true), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 300000, 25000, false), + PFUZE100_SW_REG(sw1c, PFUZE100_SW1CVOL, 300000, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 400000, 25000, true), + PFUZE100_SW_REG(sw4, PFUZE100_SW4VOL, 400000, 25000, true), PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), - PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), - PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000), - PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000), - PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000), - PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000), - PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000), + PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 1800000, 100000), }; /* PFUZE200 */ static struct pfuze100_regulator_desc pfuze200_regulators[] = { - PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 25000, false), - PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 25000, true), - PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 25000, true), - PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 25000, true), + PFUZE100_SW_REG(sw1ab, PFUZE100_SW1ABVOL, 300000, 25000, false), + PFUZE100_SW_REG(sw2, PFUZE100_SW2VOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3a, PFUZE100_SW3AVOL, 400000, 25000, true), + PFUZE100_SW_REG(sw3b, PFUZE100_SW3BVOL, 400000, 25000, true), PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), - PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 50000), - PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 50000), - PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 100000), - PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 100000), - PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 100000), - PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 100000), + PFUZE100_VGEN_REG(vgen1, PFUZE100_VGEN1VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen2, PFUZE100_VGEN2VOL, 800000, 50000), + PFUZE100_VGEN_REG(vgen3, PFUZE100_VGEN3VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen4, PFUZE100_VGEN4VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen5, PFUZE100_VGEN5VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vgen6, PFUZE100_VGEN6VOL, 1800000, 100000), }; /* PFUZE3000 */ static struct pfuze100_regulator_desc pfuze3000_regulators[] = { - PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 25000), - PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 25000), + PFUZE3000_SW1_REG(sw1a, PFUZE100_SW1ABVOL, 700000, 25000), + PFUZE3000_SW1_REG(sw1b, PFUZE100_SW1CVOL, 700000, 25000), PFUZE100_SWB_REG(sw2, PFUZE100_SW2VOL, 0x7, 50000, pfuze3000_sw2lo, true), - PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 50000), + PFUZE3000_SW3_REG(sw3, PFUZE100_SW3AVOL, 900000, 50000), PFUZE100_SWB_REG(swbst, PFUZE100_SWBSTCON1, 0x3, 50000, pfuze100_swbst, false), PFUZE100_SNVS_REG(vsnvs, PFUZE100_VSNVSVOL, 0x7, pfuze3000_vsnvs), PFUZE100_FIXED_REG(vrefddr, PFUZE100_VREFDDRCON, 750000), - PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 100000), - PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 50000), - PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 150000), - PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 150000), - PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 100000), - PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 100000), + PFUZE100_VGEN_REG(vldo1, PFUZE100_VGEN1VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vldo2, PFUZE100_VGEN2VOL, 800000, 50000), + PFUZE3000_VCC_REG(vccsd, PFUZE100_VGEN3VOL, 2850000, 150000), + PFUZE3000_VCC_REG(v33, PFUZE100_VGEN4VOL, 2850000, 150000), + PFUZE100_VGEN_REG(vldo3, PFUZE100_VGEN5VOL, 1800000, 100000), + PFUZE100_VGEN_REG(vldo4, PFUZE100_VGEN6VOL, 1800000, 100000), }; #define MODE(_id, _val, _name) { \ @@ -483,15 +491,15 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) val &= desc->vsel_mask; *uV = desc->volt_table[val]; } else { - if (uc_pdata->min_uV < 0) { - debug("Need to provide min_uV in dts.\n"); + if (uc_pdata->min_uV < desc->min_uV) { + debug("min_uV in dts can not be below regulator min_uV.\n"); return -EINVAL; } val = pmic_reg_read(dev->parent, desc->vsel_reg); if (val < 0) return val; val &= desc->vsel_mask; - *uV = uc_pdata->min_uV + (int)val * desc->uV_step; + *uV = desc->min_uV + (int)val * desc->uV_step; } return 0; @@ -513,13 +521,13 @@ static int pfuze100_regulator_val(struct udevice *dev, int op, int *uV) return pmic_clrsetbits(dev->parent, desc->vsel_reg, desc->vsel_mask, i); } else { - if (uc_pdata->min_uV < 0) { - debug("Need to provide min_uV in dts.\n"); + if (uc_pdata->min_uV < desc->min_uV) { + debug("min_uV in dts can not be below regulator min_uV.\n"); return -EINVAL; } return pmic_clrsetbits(dev->parent, desc->vsel_reg, desc->vsel_mask, - (*uV - uc_pdata->min_uV) / desc->uV_step); + (*uV - desc->min_uV) / desc->uV_step); } return 0;