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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-4a35a076597sor31830925e9.2.2026.10.28.06.59.21 for (Google Transport Security); Wed, 28 Oct 2026 06:59:21 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AKwUvBwhNjgdh273vTtHu0SpgYK444TyGsCqN6q7jv/HOrokJSrbF7cEO2IShgbMh/Nzf4+pqZya/hDYYmq7gxpS@amarulasolutions.com X-Gm-Gg: AYBFou19TG7oEg8i3CRJXbqNmBeZ1UdKc/VV39u3ROK4YcG1Xn+qwU4PtrMvzGFBQQ4 S7/laNdBfgZG8uBZ4ZN0ej+vCi+vqdGDWTdZOytnNJp94tljDmlAjVA94Db7+X1FSg8quYrp21E HzHAH2vq0LBThEEbuUyGgzAmzWt+RqjDTU9MTcBs6eb60ox7Fe8ogs9AMUKminfkCv5Gb89IhbG 80irC52h1hqvSmK/sIfMqpfXVv8dJbmOP+kBCm6740jl+KhHdvgviivx2gAIUksvaoAFRDsAMjf sgkQZKG10aIKZBXF2S/FPoQQXVH+hbZDCtPSGO/qjeOcILsSv2xMtQ+M3Dvmlbauazt/gBxigNg 6BPEHFIs3AuxjCGEShmbm9N02FzOj5b0BzhsGDnZfNXs7JVcQBYIVpfRZUoU9ZRfa/jnR6N2843 Rk5ITvzGeQpHTmUmPNgbH2fHBzCHDHdQ8jK3caUR4GgazhTVxKMhDdtqKq/r/LGjl9rHpiUeL1F +ZiHKGOsEy5ysQ6fYZQoX+6IJLLW9O5OZ5oRlNq1bMdFUkfj3Ak/X4ZPvRGIzfA1GySyYIxf1q6 NU+YnK0edHc0y+NKaARGqD6hbddgPGflUKk3KhC94guTL6UoQRLmdinxIZ33PG08Qj3Y7CYW2Bf iR/PgTQaFIyVzf0SD2YLXXvTypOb5iV67F2cXuQ/shjzAgdhwQA== X-Received: by 2002:a05:600c:8b05:b0:4a1:fa21:fd90 with SMTP id 5b1f17b1804b1-4a965ec95ebmr53037705e9.9.1793195961149; Wed, 28 Oct 2026 06:59:21 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:20 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 1/4] arm64: dts: st: fix the Engicam RMM RGB display pixel clock Date: Wed, 28 Oct 2026 14:59:05 +0100 Message-ID: <20261028135915.2665857-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=ic2QWUrF; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On STM32MP255/257 the LTDC "lcd" clock is a fixed placeholder, since with the LVDS output the pixel clock comes from the LVDS PHY. With the RGB output the pixel clock is instead the LTDC kernel clock (ck_ker_ltdc). Since no consumer references it, the clock is turned off by clk_disable_unused() and its rate is never set. As a result, the LTDC does not run and every commit times out: [CRTC:42:crtc-0] vblank wait timed out [drm] *ERROR* flip_done timed out Use ck_ker_ltdc as "lcd" clock for the RGB panel overlay. Fixes: bc7b07bda4e0 ("arm64: dts: st: support Engicam MicroGEA-STM32MP257D-RMM board") Signed-off-by: Dario Binacchi --- ...2mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso index f89641bdb23b..7be955be58ed 100644 --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso @@ -10,6 +10,7 @@ /dts-v1/; /plugin/; +#include #include #include @@ -35,6 +36,8 @@ touchscreen@38 { }; <dc { + /* RGB output: the pixel clock is the LTDC kernel clock */ + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>; From patchwork Wed Oct 28 13:59:06 2026 Content-Type: text/plain; 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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-4a94f90a6adsor4138465e9.17.2026.10.28.06.59.23 for (Google Transport Security); Wed, 28 Oct 2026 06:59:23 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AKwUvByLX7q4NtT+mfagbUzreDRLQFW2jS80kIACrhckP8IXEwz6CNncPKzJdNbYdBzPzXKIs7ktuZE7c6smZbIC@amarulasolutions.com X-Gm-Gg: AYBFou19l8V16comDD5l2Z9h3o2Cz/CyvZ3CF8pb+B8zYBdP1o5v8i8j4Iat0OP8CQx +Z2ciK+4UV/Ap5uPL5swhoZURldquoL/ylQX1uTEjA8gf7oIGUyToYoXEeGhqwz4wEt6OyXkb6R LEZmpNp+xhODGM+g3sSxivW/rJwnk24/k3540DlwqSnq6g4iJtdX9EYl8HHVSL0SLkIt3sR9av4 mp1R+2td/wXGShXYDw5jLVX/BZiMGgMO5/PyAppV/cPeCEBR68/qrshPw8EbAkzQAu64S3hCl1D u1hprB+hwQZ7bxlhpqq/t6hkbVGH8eaUDv2jk8nCQCUgTJ/AA79ESz6KfuFwlV2xftTNitVNN44 qCNyvP9Ey3YZB2GhxAecaCvBuIIlnZIINn2OWR4GXmMYBcbwc7v0tMqKg6VEOdqDP7ilC5qucVu R9eddvibe/xYPehmUefE3atFSf9dFBFTDM+m+HB2KPF5+I+qJA7Dh+tp2m9M0ZzsoXam4VBk01m J/e5reiOrJzTZoTkxwIx66Vp8X6wxP1jS9zJKh+2+deVeUMBRPHwjh6KynsTSq26oky3Xi1UWZT GgZeticrEvH9pxwM0XzoWnqqNsKEBqMWSGd7HIg3jIXSJhdJFMwdi679RXWXtO3VyLU5X5BGpf/ yfIeSpxAEsm6+/DhTaK3uMKkXvhHfG/EqsjhRgdd94H72om4A X-Received: by 2002:a05:600c:19c8:b0:4a1:d459:db4b with SMTP id 5b1f17b1804b1-4a966e2a979mr54893215e9.24.1793195963058; Wed, 28 Oct 2026 06:59:23 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:22 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Brian Masney , Jerome Brunet , Maxime Coquelin , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 2/4] clk: stm32: add STM32MP25 SYSCFG clock driver Date: Wed, 28 Oct 2026 14:59:06 +0100 Message-ID: <20261028135915.2665857-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=gtBBGsg4; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On STM32MP25 the LTDC pixel clock is selected in the SYSCFG DISPLAYCLKCR register among the DSI byte lane clock, the LVDS PHY pixel clock (reset value) and the LTDC kernel clock, the latter being the one needed by the RGB (DPI) output. The SYSCFG node already provides this clock ("#clock-cells = <0>"), referenced by the LTDC as "ref" clock, but no driver registers it, so the selection is stuck at the reset value and a display connected to the LTDC RGB output can't work. Add a driver registering this clock as a mux. The SYSCFG node is already bound to the STM32MP2 SYSCFG driver, so the clock driver is bound to an auxiliary device created by the latter, which shares the SYSCFG node and regmap. Signed-off-by: Dario Binacchi --- drivers/clk/stm32/Kconfig | 12 +++ drivers/clk/stm32/Makefile | 1 + drivers/clk/stm32/clk-stm32mp25-syscfg.c | 111 +++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 drivers/clk/stm32/clk-stm32mp25-syscfg.c diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig index 5dbd75cde657..906044aacaa1 100644 --- a/drivers/clk/stm32/Kconfig +++ b/drivers/clk/stm32/Kconfig @@ -39,5 +39,17 @@ config COMMON_CLK_STM32MP257 help Support for stm32mp25x SoC family clocks. +config COMMON_CLK_STM32MP25_SYSCFG + tristate "Clock driver for stm32mp25x SYSCFG clocks" + depends on COMMON_CLK_STM32MP257 + select AUXILIARY_BUS + select MFD_SYSCON + default COMMON_CLK_STM32MP257 + help + Support for the clocks provided by the stm32mp25x SYSCFG, i.e. + the LTDC pixel clock source selection between the LTDC kernel + clock (RGB output), the LVDS PHY pixel clock and the DSI byte + lane clock. + endif diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile index e04727b59449..8088d172651f 100644 --- a/drivers/clk/stm32/Makefile +++ b/drivers/clk/stm32/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-st obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o obj-$(CONFIG_COMMON_CLK_STM32MP215) += clk-stm32mp21.o clk-stm32-core.o reset-stm32.o obj-$(CONFIG_COMMON_CLK_STM32MP257) += clk-stm32mp25.o clk-stm32-core.o reset-stm32.o +obj-$(CONFIG_COMMON_CLK_STM32MP25_SYSCFG) += clk-stm32mp25-syscfg.o diff --git a/drivers/clk/stm32/clk-stm32mp25-syscfg.c b/drivers/clk/stm32/clk-stm32mp25-syscfg.c new file mode 100644 index 000000000000..1cb2459f0370 --- /dev/null +++ b/drivers/clk/stm32/clk-stm32mp25-syscfg.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STM32MP25 SYSCFG clocks + * + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCFG_DISPLAYCLKCR 0x5000 +#define DISPLAYCLKCR_DPIVSLVDS GENMASK(1, 0) + +/* + * The LTDC pixel clock source is selected in SYSCFG_DISPLAYCLKCR among + * the DSI byte lane clock, the LVDS PHY pixel clock (reset value) and + * the LTDC kernel clock, which is used with the RGB (DPI) output. + */ +static const char * const clk_pix_ltdc_parents[] = { + "txbyteclk", "clk_pix_lvds", "ck_ker_ltdc", +}; + +struct stm32mp25_syscfg_mux { + struct clk_hw hw; + struct regmap *regmap; +}; + +static inline struct stm32mp25_syscfg_mux *to_syscfg_mux(struct clk_hw *hw) +{ + return container_of(hw, struct stm32mp25_syscfg_mux, hw); +} + +static u8 stm32mp25_syscfg_mux_get_parent(struct clk_hw *hw) +{ + struct stm32mp25_syscfg_mux *mux = to_syscfg_mux(hw); + unsigned int val; + + regmap_read(mux->regmap, SYSCFG_DISPLAYCLKCR, &val); + + return FIELD_GET(DISPLAYCLKCR_DPIVSLVDS, val); +} + +static int stm32mp25_syscfg_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct stm32mp25_syscfg_mux *mux = to_syscfg_mux(hw); + + return regmap_update_bits(mux->regmap, SYSCFG_DISPLAYCLKCR, + DISPLAYCLKCR_DPIVSLVDS, + FIELD_PREP(DISPLAYCLKCR_DPIVSLVDS, index)); +} + +static const struct clk_ops stm32mp25_syscfg_mux_ops = { + .get_parent = stm32mp25_syscfg_mux_get_parent, + .set_parent = stm32mp25_syscfg_mux_set_parent, + .determine_rate = clk_hw_determine_rate_no_reparent, +}; + +static int stm32mp25_syscfg_clk_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev = &adev->dev; + struct clk_init_data init = { }; + struct stm32mp25_syscfg_mux *mux; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + mux->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(mux->regmap)) + return dev_err_probe(dev, PTR_ERR(mux->regmap), + "failed to get the SYSCFG regmap\n"); + + init.name = "clk_pix_ltdc"; + init.ops = &stm32mp25_syscfg_mux_ops; + init.parent_names = clk_pix_ltdc_parents; + init.num_parents = ARRAY_SIZE(clk_pix_ltdc_parents); + init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT; + mux->hw.init = &init; + + ret = devm_clk_hw_register(dev, &mux->hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register %s\n", + init.name); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw); +} + +static const struct auxiliary_device_id stm32mp25_syscfg_clk_ids[] = { + { .name = "stm32mp2_syscfg.clk" }, + { } +}; +MODULE_DEVICE_TABLE(auxiliary, stm32mp25_syscfg_clk_ids); + +static struct auxiliary_driver stm32mp25_syscfg_clk_driver = { + .probe = stm32mp25_syscfg_clk_probe, + .id_table = stm32mp25_syscfg_clk_ids, +}; +module_auxiliary_driver(stm32mp25_syscfg_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("STM32MP25 SYSCFG clock driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Oct 28 13:59:07 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 4904 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id A2EA43F130 for ; Wed, 28 Oct 2026 14:59:27 +0100 (CET) Received: by mail-wr1-f70.google.com with SMTP id ffacd0b85a97d-48c4445512dsf909960f8f.2 for ; Wed, 28 Oct 2026 06:59:27 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1793195967; cv=pass; d=google.com; s=arc-20260327; b=X/OTYFYDBgEy9r62B71rwNzi0de9p3YgmchfIdZonxKNLY0wsJmxOJ3GbluF1TKy3y 2Sb+JycWrbu9U4nXlyHP6EHLFBoVQAAOUSS0BijsurC4wDuM4o9soJkmYt7jAUWJu32J 31I4rCuN8D08iV0qgX8NUDEzP3H1GlQ+CWRIqD96yl1NgsHWPYOkee9vKD2X4KFTK/x4 QIieFx9LOfKXCU/PW9V58TUCKSEC9L2ZZ+TyV9tPW42b6eUaE0P/20jkfl/V3BXOejR7 iDNGW3F3jU6BcCd52EbbSVAltnlCAyMWTtQWcg1fpdz/H9HsorHIJvtQ86oqq7fyB9sa sURw== ARC-Message-Signature: i=2; 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Create the auxiliary device for the clock driver on STM32MP25. Signed-off-by: Dario Binacchi --- drivers/soc/st/Kconfig | 1 + drivers/soc/st/stm32mp2-syscfg.c | 28 ++++++++++++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/soc/st/Kconfig b/drivers/soc/st/Kconfig index 2a9d6a77be45..62bbe8c63238 100644 --- a/drivers/soc/st/Kconfig +++ b/drivers/soc/st/Kconfig @@ -5,6 +5,7 @@ config SOC_STM32MP2 tristate "STM32MP2 SoC family support" depends on ARCH_STM32 || COMPILE_TEST default ARCH_STM32 && ARM64 + select AUXILIARY_BUS select SOC_BUS help If you say yes here, you get support for the ST STM32MP2 family diff --git a/drivers/soc/st/stm32mp2-syscfg.c b/drivers/soc/st/stm32mp2-syscfg.c index 770321a4a6f7..300a949744c5 100644 --- a/drivers/soc/st/stm32mp2-syscfg.c +++ b/drivers/soc/st/stm32mp2-syscfg.c @@ -3,18 +3,42 @@ * Copyright 2026 Marek Vasut */ +#include #include #include #include +#include + +struct stm32mp2_syscfg_data { + bool has_clk; +}; static int stm32mp2_syscfg_probe(struct platform_device *pdev) { - return devm_of_platform_populate(&pdev->dev); + const struct stm32mp2_syscfg_data *data; + struct device *dev = &pdev->dev; + int ret; + + ret = devm_of_platform_populate(dev); + if (ret) + return ret; + + data = device_get_match_data(dev); + if (data && data->has_clk && + !devm_auxiliary_device_create(dev, "clk", NULL)) + return dev_err_probe(dev, -ENODEV, + "failed to register the clock device\n"); + + return 0; } +static const struct stm32mp2_syscfg_data stm32mp25_syscfg_data = { + .has_clk = true, +}; + static const struct of_device_id stm32mp2_syscfg_ids[] = { { .compatible = "st,stm32mp23-syscfg" }, - { .compatible = "st,stm32mp25-syscfg" }, + { .compatible = "st,stm32mp25-syscfg", .data = &stm32mp25_syscfg_data }, { } }; MODULE_DEVICE_TABLE(of, stm32mp2_syscfg_ids); From patchwork Wed Oct 28 13:59:08 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 4905 Return-Path: X-Original-To: linux-amarula@patchwork.amarulasolutions.com Delivered-To: linux-amarula@patchwork.amarulasolutions.com Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by ganimede.amarulasolutions.com (Postfix) with ESMTPS id 604353F130 for ; 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[209.85.220.41]) by mx.google.com with SMTPS id 5b1f17b1804b1-4a35a423542sor22306355e9.17.2026.10.28.06.59.27 for (Google Transport Security); Wed, 28 Oct 2026 06:59:27 -0700 (PDT) Received-SPF: pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) client-ip=209.85.220.41; X-Forwarded-Encrypted: i=1; AKwUvBwkJiGcjt3IMxDL5cLUG8TkwHE2u+tW10Nk+I25gJIv7kkLbD4vN9MCvB3p1OdG+IclTTDuQdE3xt5CO4Pk@amarulasolutions.com X-Gm-Gg: AYBFou0meUBw9Rlimn8NxN3R4XDP7BSWf7861zA5/kdmeyZht4NImWMP+5wD9mUr92T FeZDAVD0AjdYVw6RRC2Xg+UtB5qpeTFtel+LQee7ZRPbvA3zWVI7dt/sTR4kTrI+ftw46AO7MsB 0/sTtJjdhsQIP3VziSCCmYU5OFrt4VNdS5GSmKM6lgXyRWKSI51f20UUxllEx6AdTpSN195gXpR DUjndkwz+eKhl/2rkJGb2SPl/Kd+eoWzv+/2hoSYEPKT0f62Iag1fQ6vGTwQu4tBR1Zo5cdjC2U O7wouTbDpGVrHEevB5k8oCR8i+RSWJhd2xwIP8Pwy0Uw/M/6HlrziCpf2mmwEKKSFNHDh6lgnRB 9zZvb1fwgS4HmRwU6M5gDYRTPATk2DUIbGkNdUxEvf/lFPTvP5BLNCWJ/wGgMQdPYp/tCeHKoNU X1zDferAsNzoxZsHJQJoxJqGKpgi9gag/Y7i9EaGhMKi+aJPziHDCb7NnXF4dc1fg5RwxgL63a9 JF+x2PRBJDCDUd/ilGVQtak7qJ2n9wbuzD7K5YJ02s+zj0Sz5IRqDJWSGEYKp+MjWa6qBgXgZJK poHAV2YFLtj//vJU0RVI5WwZt7LMpbi/xaGvvzh2jEd+Fqf2J/neltPBpvtLEUcY9ig7LRkLE3H F55CF4sBsrAvrUpCsuHUZEn5LOK0DUfWv7IK27YVOfCHbJVY5+cfCjHeWag+UjhzLvBH8VQ== X-Received: by 2002:a05:600c:3512:b0:4a2:c9b:9b98 with SMTP id 5b1f17b1804b1-4a9665876a3mr51801145e9.17.1793195966837; Wed, 28 Oct 2026 06:59:26 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.amarulasolutions.com ([2.196.42.39]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94f05f168sm37077165e9.4.2026.10.28.06.59.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 06:59:26 -0700 (PDT) From: Dario Binacchi To: Alexandre Torgue , Stephen Boyd Cc: Marek Vasut , Gabriel Fernandez , michael@amarulasolutions.com, linux-amarula@amarulasolutions.com, Yannick Fertre , Raphael Gallais-Pou , Dario Binacchi , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH 4/4] arm64: dts: st: select the Engicam RMM display pixel clock source Date: Wed, 28 Oct 2026 14:59:08 +0100 Message-ID: <20261028135915.2665857-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> References: <20261028135915.2665857-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 X-Original-Sender: dario.binacchi@amarulasolutions.com X-Original-Authentication-Results: mx.google.com; dkim=pass header.i=@amarulasolutions.com header.s=google header.b=czky9GMC; spf=pass (google.com: domain of dario.binacchi@amarulasolutions.com designates 209.85.220.41 as permitted sender) smtp.mailfrom=dario.binacchi@amarulasolutions.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=amarulasolutions.com; dara=neutral header.i=@amarulasolutions.com Precedence: list Mailing-list: list linux-amarula@amarulasolutions.com; contact linux-amarula+owners@amarulasolutions.com List-ID: X-Spam-Checked-In-Group: linux-amarula@amarulasolutions.com X-Google-Group-Id: 476853432473 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On STM32MP255/257 the LTDC pixel clock is selected by the SYSCFG pixel clock mux, whose reset value is the LVDS PHY pixel clock. With the RGB panel the LTDC is then clocked by the unused LVDS PHY, and every commit times out: [CRTC:42:crtc-0] vblank wait timed out [drm] *ERROR* flip_done timed out Select the LTDC kernel clock as pixel clock source in the RGB panel overlay and, for consistency, without relying on the reset value, the LVDS PHY pixel clock in the LVDS panel overlay. Signed-off-by: Dario Binacchi --- ...57d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso | 3 +++ ...2mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso index 7655c1bf56b1..b44e1d3ddb1b 100644 --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-am-1280800w8tzqw-t00h.dtso @@ -32,6 +32,9 @@ &framebuffer { }; <dc { + /* LVDS output: the pixel clock is the LVDS PHY one */ + assigned-clocks = <&syscfg>; + assigned-clock-parents = <&lvds>; status = "okay"; port { diff --git a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso index 7be955be58ed..7855086c33c7 100644 --- a/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso +++ b/arch/arm64/boot/dts/st/stm32mp257d-engicam-microgea-rmm-overlay-rk050hr345-ct106a.dtso @@ -38,6 +38,8 @@ touchscreen@38 { <dc { /* RGB output: the pixel clock is the LTDC kernel clock */ clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + assigned-clocks = <&syscfg>; + assigned-clock-parents = <&rcc CK_KER_LTDC>; pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; pinctrl-1 = <<dc_sleep_pins_a>;